Gate-all-around integrated circuit structures having depopulated channel structures using directed bottom-up approach

A method of fabricating an integrated circuit structure, the method comprising:

• forming a vertical arrangement of nanowires;
• forming a gate stack over and around the vertical arrangement of nanowires, wherein a bottommost surface of the gate stack is below a bottommost nanowire of the vertical arrangement of nanowires;
• forming a first epitaxial source or drain structure at a first end of the vertical arrangement of nanowires;
• forming a second epitaxial source or drain structure at a second end of the vertical arrangement of nanowires, the second end opposite the first end, wherein one of the first or second epitaxial source or drain structures is coupled to fewer than all nanowires of the vertical arrangement of nanowires;
• forming a liner dielectric layer having an internal spacer portion between nanowires of the vertical arrangement of nanowires, and a cavity liner portion beneath the one of the first or second epitaxial source or drain structures, the cavity liner portion continuous with the internal spacer portion.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a vertical arrangement of nanowires;
• a gate stack over and around the vertical arrangement of nanowires, wherein a bottommost surface of the gate stack is below a bottommost nanowire of the vertical arrangement of nanowires;
• a first epitaxial source or drain structure at a first end of the vertical arrangement of nanowires;
• a second epitaxial source or drain structure at a second end of the vertical arrangement of nanowires, the second end opposite the first end, wherein one of the first or second epitaxial source or drain structures is coupled to fewer than all nanowires of the vertical arrangement of nanowires;
• and
• a liner dielectric layer having an internal spacer portion between nanowires of the vertical arrangement of nanowires, and a cavity liner portion beneath the one of the first or second epitaxial source or drain structures, the cavity liner portion continuous with the internal spacer portion.