Multi-gate device and manufacturing method thereof

A method, comprising:

• forming an isolation feature over a substrate;
• forming a fin-shaped structure protruding from the substrate and through the isolation feature, the fin-shaped structure comprising a plurality of channel layers interleaved by a plurality of sacrificial layers, a topmost one of the channel layers positioned under a topmost one of the sacrificial layers;
• forming a sacrificial gate structure across the fin-shaped structure;
• depositing a gate sidewall spacer extending along a sidewall of the sacrificial gate structure;
• removing the sacrificial gate structure to form a gate trench;
• removing the sacrificial layers form the gate trench, the removing of the sacrificial layers exposing a bottom surface of the gate sidewall spacer;
• and
• depositing a metal gate structure in the gate trench, the metal gate structure including a first portion above the topmost one of the channel layers and a second portion in gaps between adjacent ones of the channel layers, an interface between the first portion of the metal gate structure and the bottom surface of the gate sidewall spacer having a slope profile.

A semiconductor device, comprising:

• a plurality of semiconductor nanostructures disposed over a substrate;
• an epitaxial feature abutting the semiconductor nanostructures;
• a metal gate structure wrapping around at least one of the semiconductor nanostructures, wherein the metal gate structure includes a gate dielectric layer and a gate electrode over the gate dielectric layer;
• and
• a gate spacer extending along a sidewall of the metal gate structure,
• wherein a dielectric constant of the gate dielectric layer is greater than a dielectric constant of the gate spacer, and wherein a first portion of the metal gate structure has a bottom surface between a top surface of a topmost semiconductor nanostructure and a bottom surface of the gate spacer.