US 2026/0282393 A1Published application

Semiconductor device including dummy pad

AssigneeSamsung Electronics Co., Ltd.

InventorsInhyo Hwang, Young Lyong Kim, Hyunsoo Chung

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Abstract

A method of fabricating semiconductor package device includes: preparing a first wafer and a second wafer; positioning the second wafer on the first wafer; and bonding the first wafer and the second wafer, the first wafer including: a first substrate having a first surface and a second surface; a first insulating structure; electrode layers and inter-electrode insulating layers on the first wafer,; vertical semiconductor patterns; first metal pads disposed on a top of the first insulating structure; and first dummy pads disposed on a top of the first insulating structure, the second wafer including: a second substrate having a third surface and a fourth surface; a second insulating structure; second metal pads disposed on a top of the second insulating structure; and second dummy pads disposed on a top of the second insulating structure.

Claims20

Dependent claims

A method of fabricating semiconductor package device, comprising:

preparing a first wafer and a second wafer, each of the first wafer and the second wafer includes a device region and a scribe lane region;
positioning the second wafer on the first wafer so that the device region of the second wafer overlaps the device region of the first wafer;
and
bonding the first wafer and the second wafer,
wherein the first wafer includes:
a first substrate having a first surface and a second surface facing the first surface;
a first insulating structure on the first surface of the first substrate;
electrode layers and inter-electrode insulating layers on the device region of the first wafer, the electrode layers and the inter-electrode insulating layers being alternately stacked between the first surface of the first substrate and the first insulating structure;
vertical semiconductor patterns adjacent to the first substrate through the inter-electrode insulating layers and the electrode layers;
first metal pads disposed on a top of the first insulating structure on the device region of the first wafer;
and
first dummy pads disposed on a top of the first insulating structure on the scribe lane region of the first wafer, wherein the second wafer includes:
a second substrate having a third surface and a fourth surface facing the third surface;
a second insulating structure on the third surface of the second substrate;
second metal pads disposed on a top of the second insulating structure on the device region of the second wafer;
and
second dummy pads disposed on a top of the second insulating structure on the scribe lane region of the second wafer,
wherein positioning the second wafer on the first wafer includes arranging the third surface of the second wafer to face the first surface of the first wafer,
wherein bonding the first wafer and the second wafer includes:
bonding the first metal pads and the second metal pads;
and
bonding the first dummy pads and the second dummy pads.

19 more elements

A method of fabricating semiconductor package device, comprising:

preparing a first wafer and a second wafer, each of the first wafer and the second wafer includes a device region and a scribe lane region;
positioning the second wafer on the first wafer so that the device region of the second wafer overlaps the device region of the first wafer;
and
bonding the first wafer and the second wafer,
wherein the first wafer includes:
a first substrate;
a first insulating structure on the first substrate;
first metal pads disposed on a top of the first insulating structure on the device region of the first wafer;
first dummy pads disposed on a top of the first insulating structure on the scribe lane region of the first wafer;
a first interconnection structure disposed in the first insulating structure, the first interconnection structure being electrically connected to the first metal pads;
and
a first guard ring structure extending into the first insulating structure on the scribe lane region of the first wafer,
wherein the second wafer includes:
a second substrate;
a second insulating structure on the second substrate;
second metal pads disposed on a top of the second insulating structure on the device region of the second wafer;
second dummy pads disposed on a top of the second insulating structure on the scribe lane region of the second wafer;
a second interconnection structure disposed in the second insulating structure, the second interconnection structure being electrically connected to the second metal pads;
and
a second guard ring structure extending into the second insulating structure on the scribe lane region of the second wafer, wherein bonding the first wafer and the second wafer includes:
bonding the first metal pads and the second metal pads;
and
bonding the first dummy pads and the second dummy pads.

20 more elements

A method of fabricating semiconductor package device, comprising:

preparing a first wafer and a second wafer, each of the first wafer and the second wafer includes a device region and a scribe lane region;
positioning the second wafer on the first wafer so that the device region of the second wafer overlaps the device region of the first wafer;
bonding the first wafer and the second wafer;
and
separating the first wafer and the second wafer bonded to each other into semiconductor devices,
wherein the first wafer includes:
a first substrate;
a first insulating structure on the first substrate;
first metal pads disposed on a top of the first insulating structure on the device region of the first wafer;
first dummy pads disposed on a top of the first insulating structure on the scribe lane region of the first wafer;
a first interconnection structure disposed in the first insulating structure, the first interconnection structure being electrically connected to the first metal pads;
a first guard ring structure extending into the first insulating structure on the scribe lane region of the first wafer;
and
a scattering beam blocking pattern in the first insulating structure on the scribe lane region of the first wafer,
wherein the second wafer includes:
a second substrate;
a second insulating structure on the second substrate;
second metal pads disposed on a top of the second insulating structure on the device region of the second wafer;
second dummy pads disposed on a top of the second insulating structure on the scribe lane region of the second wafer;
and
a second interconnection structure disposed in the second insulating structure, the second interconnection structure being electrically connected to the second metal pads, wherein bonding the first wafer and the second wafer includes:
bonding the first metal pads and the second metal pads;
and
bonding the first dummy pads and the second dummy pads.

21 more elements

Dependencies are inferred from the claim text.

Facts

Application: 19/556,938Filed 4 Mar 2026
Priority: KR 10-2022-00813751 Jul 2022
Published: 17 Sep 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification22 codes

H10B 43/40
EEPROM devices comprising charge-trapping gate insulators: characterised by the peripheral circuit region
H10B 80/00
Assemblies of multiple devices comprising at least one memory device covered by
H10P 54/00
Cutting or separating of wafers, substrates or parts of devices
H10P 74/203
Characterised by the properties tested or measured, e.g. structural or electrical properties: structural properties, e.g. testing or measuring…

Family

Application18/181,731Continuation · filed 10 Mar 2023
Application19/556,938Continuation
US 12,598,758 B2Related patent
US 2024/0006356 A1Published application
US 2026/0282393 A1This patent

From the US filing history. Foreign family members aren’t listed.