3d ferroelectric memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsJinseong HEO, Taehwan MOON, Seunggeol NAM, Hyunjae LEE
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Abstract
Provided is a 3D ferroelectric memory device. The 3D ferroelectric memory device may include a plurality of gate electrodes stacked on a substrate in a first direction; a plurality of ferroelectric layers on the plurality of gate electrodes in a second direction; a plurality of intermediate electrodes on the plurality of ferroelectric layers in the second direction; a first insulating layer between the plurality of gate electrodes and between the plurality of intermediate electrodes; a second insulating layer on the plurality of intermediate electrodes and the first insulating layer; and a channel layer on the second insulating layer.
Claims15
A method of manufacturing a semiconductor device, the method comprising:
- alternately stacking a plurality of first insulating layers and a plurality of sacrificial layers on a substrate;
- forming a channel hole through the plurality of first insulating layers and the plurality of sacrificial layers;
- forming a plurality of first recesses by etching the plurality of sacrificial layers exposed through the channel hole to a given depth;
- forming a plurality of second recesses by etching portions of the plurality of first insulating layers exposed through the plurality of first recesses;
- forming a plurality of intermediate electrodes to fill the plurality of second recesses;
- depositing a second insulating layer and a channel layer on an inner wall of the channel hole;
- removing the plurality of sacrificial layers;
- depositing a plurality of ferroelectric layers on inner walls of spaces from which the plurality of sacrificial layers are removed;
- and
- forming a plurality of gate electrodes inside the plurality of ferroelectric layers.
Dependencies are inferred from the claim text.