Mim memory cell with backside interconnect structures
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMeng-Sheng Chang, Chia-En Huang, Yih Wang
Life of this patent
Estimating the term…
Abstract
A memory device is disclosed. The memory device includes a plurality of one-time programmable (OTP) memory cells. Each OTP memory cell includes a transistor disposed on a first side of a substrate, and a capacitor disposed on a second side of the substrate opposite to the first side and electrically connected to the transistor. The capacitor includes a first terminal, a second terminal formed vertically lower than the first terminal, and an insulation layer vertically interposed therebetween.
Claims20
A memory device, comprising:
- a one-time programmable (OTP) memory cell comprising:
- a capacitor disposed on a substrate and electrically connected to a transistor,
- wherein the capacitor comprises a first terminal including a first interconnect metal via that is electrically connected to a source/drain structure of the transistor, a second terminal including a first interconnect metal line that is electrically connected to a bit line, and an insulation layer interposed therebetween.
A memory device, comprising:
- a capacitor disposed on a substrate and comprising a first terminal, a second terminal formed vertically lower than the first terminal, and an insulation layer interposed therebetween and electrically connected to a transistor;
- and
- a plurality of interconnect structures, comprising:
- a first interconnect structure configured to serve as the first terminal of the capacitor and including a metal via electrically connected to a source/drain structure of the transistor, and
- a second interconnect structure configured to serve as the second terminal of the capacitor and including a metal line electrically connected to a bit line.
A memory device, comprising:
- a capacitor disposed on a first side of a substrate and comprising a first terminal, a second terminal, and an insulation layer interposed therebetween,
- wherein the first terminal includes a first interconnect metal via that is electrically connected to a source/drain terminal contact of a source/drain terminal of a transistor from a back side of the source/drain terminal contact, and the second terminal includes a first interconnect metal line that is electrically connected to a bit line on a second, opposite side of the substrate.
Dependencies are inferred from the claim text.