In-sensor multiply-and-accumulate pixel sensor circuit assembly

An in-sensor multiply-and-accumulate (MAC) pixel sensor circuit assembly for an image sensor, the circuit assembly comprising:

• a first transistor;
• a ferroelectric field-effect transistor (FeFET) electrically coupled with said first transistor;
• and
• a pixel selector transistor electrically coupled with said first transistor;
• wherein, amid use of the in-sensor multiply-and-accumulate pixel sensor circuit assembly, multiply-and-accumulate operations of the in-sensor multiply-and-accumulate pixel sensor circuit assembly are executed wholly at the in-sensor multiply-and-accumulate pixel sensor circuit assembly;
• wherein, amid use of the in-sensor multiply-and-accumulate pixel sensor circuit assembly, during a reset phase of an active weight cycle of the in-sensor multiply-and-accumulate pixel sensor circuit assembly, a negative gate pulse is applied to said ferroelectric field-effect transistor in order to reset said ferroelectric field-effect transistor, and subsequently a positive gate pulse is applied to said ferroelectric field-effect transistor in order to set a polarization amount of said ferroelectric field-effect transistor;
• and
• wherein, amid use of the in-sensor multiply-and-accumulate pixel sensor circuit assembly, during an inactive weight cycle of the in-sensor multiply-and-accumulate pixel sensor circuit assembly, said ferroelectric field-effect transistor is deactivated.

An in-sensor multiply-and-accumulate (MAC) pixel sensor circuit assembly for an image sensor, the circuit assembly comprising:

• a first transistor;
• a ferroelectric field-effect transistor (FeFET) electrically coupled with said first transistor, wherein a terminal of said ferroelectric field-effect transistor transfers a polarization charge value of said ferroelectric field-effect transistor during use of the in-sensor multiply-and-accumulate pixel sensor circuit assembly;
• and
• a pixel selector transistor electrically coupled with said first transistor;
• wherein, amid use of the in-sensor multiply-and-accumulate pixel sensor circuit assembly, multiply-and-accumulate operations of the in-sensor multiply-and-accumulate pixel sensor circuit assembly are executed wholly at the in-sensor multiply-and-accumulate pixel sensor circuit assembly;
• and
• wherein, amid use of the in-sensor multiply-and-accumulate pixel sensor circuit assembly, a programming voltage amplitude of said ferroelectric field-effect transistor is varied in order to effect various levels of remnant polarizations of said ferroelectric field-effect transistor and providing variations in conductance of said ferroelectric field-effect transistor.