Digital-to-analog circuit calibration for a successive approximation register analog-to-digital converter

Abstract

An analog-to-digital converter includes a first capacitive digital-to-analog converter (DAC) having a first plurality of binary weighted capacitors, a first calibration DAC having a first plurality of variable capacitors, each variable capacitor being configured to be coupled in parallel with a corresponding capacitor in the first plurality of binary weighted capacitors, a second capacitive DAC having a second plurality of binary weighted capacitors, a second calibration DAC having a second plurality of variable capacitors, each variable capacitor being configured for coupling in parallel with a corresponding capacitor in the second plurality of binary weighted capacitors, and calibration logic configured to provide control signals that select a capacitance for each of the first plurality of variable capacitors and the second plurality of variable capacitors based on a calibration signal that is representative of differences between outputs of the first capacitive DAC and the second capacitive DAC.

Dependencies are inferred from the claim text.