PLL Lock Detector Circuit

A lock-detection circuit for use in a phase-locked loop or a delay-locked loop, the lock-detection circuit comprising:

• a first signal-duration filter configured to receive an up signal (UP) and to output a filtered UP signal that includes a part of the UP signal that exceeds a minimum duration;
• a second signal-duration filter configured to receive a down signal (DN) and to output a filtered DN signal that includes a part of the DN signal that exceeds the minimum duration;
• a filter logic circuit with inputs coupled with an output of the first signal-duration filter and an output of the second signal-duration filter, and configured to assert a filter logic circuit output when the filtered UP signal and/or the filtered DN signal is asserted;
• and
• a first timer with a start/reset input coupled with an output of the filter logic circuit and configured to assert a LOCK detected signal a wait time after the start/reset input was most recently asserted;
• wherein:
• the minimum duration is longer than a spike in the UP signal, including a spike broadened by jitter, and longer than a spike in the DN signal, including a spike broadened by jitter;
• and
• the minimum duration is longer than an expected duration of a phase error correcting pulse when the phase-locked loop or the delay-locked loop is in lock.