Phase locked loop circuit with time interleaved phase frequency detectors

A transceiver comprising two or more Phase Locked Loop, PLL, circuits, each of the two or more PLL circuits comprising:

• a digitally controlled oscillator, DCO, configured to generate an output signal;
• an integer number M of Phase Frequency Detectors, PFDs, each PFD having a first input, a second input and a first output and a second output, one of the M PFDs being a master PFD;
• M Time to Digital Converters, TDCs, connected to the outputs of the M PDFs respectively, the TDC connected to the master PFD being configured to:
• detect whether a significant pulse with a polarity of either positive or negative is generated at the output of the master PFD, a pulse being significant means a duration length of the pulse is larger than a threshold;
• and
• if a significant pulse is detected, generate a force signal to other PFDs to enforce the other PFDs to generate output pulses with the same polarity as that of the master PFD;
• a first frequency divider configured to receive a reference signal and frequency divide the reference signal by M to generate M frequency-divided reference signals shifted in time by one period Tr of the reference signal from each other, wherein the M frequency-divided reference signals are input to the first inputs of the M PFDs respectively;
• a second frequency divider configured to receive a feedback signal and frequency divide the feedback signal by M to generate M frequency-divided feedback signals shifted in time by one period Tf of the feedback signal from each other, the M frequency-divided feedback signals being input to the second inputs of the M PFDs respectively;
• a third frequency divider configured to receive the output signal from the DCO and frequency divide the output signal from the DCO to generate the feedback signal to the second frequency divider;
• a digital processing unit configured to receive signals from the M TDCs and generate an output signal per cycle of the reference signal based on the received signals from the M TDCs;
• and
• a loop filter configured to receive the output signal from the digital processing unit and generate a control signal to the DCO to adjust the frequency of the output signal generated from the DCO.

A method performed in a Phase Locked Loop, PLL, circuit for generating an output signal comprising:

• generating M frequency-divided reference signals by a first frequency divider configured to receive a reference signal and frequency divide the reference signal by M, wherein the M frequency-divided reference signals are shifted in time by one period Tr of the reference signal from each other;
• receiving the M frequency-divided reference signals at first inputs of M Phase Frequency Detectors, PFDs respectively;
• generating M frequency-divided feedback signals by a second frequency divider configured to receive a feedback signal and frequency divide the feedback signal by M, wherein the M frequency-divided feedback signals are shifted in time by one period Tf of the feedback signal from each other;
• receiving the M frequency-divided feedback signals at second inputs of the M PFDs respectively;
• generating the feedback signal to the second frequency divider by a third frequency divider configured to receive an output signal from a digitally controlled oscillator, DCO and frequency divide the output signal from the DCO;
• receiving signals from the M PFDs by M TDCs;
• detecting by a TDC, whether a significant pulse with a polarity of either positive or negative is generated at the output of a master PFD, a pulse being significant means a duration length of the pulse is larger than a threshold;
• if a significant pulse is detected, generating a force signal by the TDC, to other PFDs to enforce the other PFDs to generate output pulses with the same polarity as that of the master PFD;
• receiving signals from the M TDCs by a digital processing unit;
• generating an output signal per cycle of the reference signal by the digital processing unit based on the received signals from the M TDCs;
• receiving the output signal from the digital processing unit by a loop filter;
• generating a control signal by the loop filter to the DCO;
• and
• receiving the control signal and generating an output signal by the DCO, wherein the frequency of the output signal generated from the DCO is adjusted by the control signal.