US 2026/0280567 A1 · CLOCK AND DATA RECOVERY FOR HIGH-SPEED SERIAL COMMUNICATION APPLICATIONS

Abstract

An apparatus for clock and data recovery (CDR) from a high-speed serial data stream is configured to operate over a wide range of data rates without the use of voltage-controlled oscillators (VCOs) or variable-delay gates (as in a delay-locked loop). The clock may be centered within the data eye by detecting the phase relationship between the data and clock with an at-rate 2- or 4-quadrant phase detector driving an analog loop filter, low-speed digital control loop, and phase interpolator. The phase interpolator may rotate the reference clock to be centered within the data eye for a low bit error rate. The CDR may track out frequency errors between the reference clock and incoming data stream without losing lock or loss of data. In integrated circuit implementations, the CDR consumes low die area due to the lack of VCOs.

Claims20

Dependent claims

An apparatus comprising:

a first memory element coupled to a first exclusive OR (XOR) gate configured to generate a first output;
a second memory element coupled to a second XOR gate configured to generate a second output;
and
a first variable capacitor coupled to the first XOR gate and the second XOR gate, the first variable capacitor configured to combine the first output and the second output and to provide an analog output to a comparator;
wherein an input of the first memory element is configured to receive a high-speed data signal input;
and
wherein an input of the second memory element is configured to receive the high-speed data signal input.

4 more elements

A system comprising:

an amplifier configured to receive and amplify a data input signal to produce a high-speed data signal;
a phase detector configured to convert the high-speed data signal to an analog signal, the phase detector comprising:
a first memory element coupled to a first exclusive OR (XOR) gate configured to generate a first output;
and
a second memory element coupled to a second XOR gate configured to generate a second output;
wherein an input of the first memory element is coupled to the amplifier and configured to receive the high-speed data signal;
and
wherein an input of the second memory element is coupled to the amplifier and configured to receive the high-speed data signal;
a single de-multiplexor coupled to the input of the first memory element and the input of the second memory element and configured to receive the high-speed data signal;
a comparator coupled to one or more outputs of the phase detector and an up/down counter and configured to produce a low-speed digital signal;
and
a phase interpolator coupled to an output of the up/down counter and configured to provide a phase interpolator output to a first memory element input of the first memory element and a second memory element input of the second memory element.

9 more elements

A method comprising:

providing a high-speed data signal to a phase detector, the phase detector comprising:
a first memory element coupled to a first exclusive OR (XOR) gate configured to generate a first output;
and
a second memory element coupled to a second XOR gate configured to generate a second output;
wherein an input of the first memory element is coupled to an amplifier and configured to receive the high-speed data signal;
and
wherein an input of the second memory element is coupled to the amplifier and configured to receive the high-speed data signal;
providing a phase interpolator output to the phase detector using a phase interpolator;
generating one or more analog signals using the phase detector based on the high-speed data signal and the phase interpolator output;
providing the one or more analog signals to a comparator to generate a low-speed digital signal;
providing the low-speed digital signal to the phase interpolator;
and
adjusting the phase interpolator output based on the low-speed digital signal.

10 more elements

Dependencies are inferred from the claim text.

Clock and data recovery for high-speed serial communication applications

Life of this patent

Clock and data recovery for high-speed serial communication applications

Life of this patent

Abstract

Claims20