Digital duty cycle corrector circuit
OwnerChang-Yi Liinventor
Life of this patent
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Abstract
A digital duty cycle corrector circuit is provided. The duty cycle corrector circuit includes a control circuit having a first transistor and a second transistor connected at a first node and configured to adjust a duty cycle of an input clock received at the first node and provide a duty adjusted output clock at a second node. A single to differential circuit is connected to the control circuit at the second node. The single to differential circuit generates a first output clock and a second output clock from the duty adjusted output clock. A feedback circuit configured to provide the duty adjusting output clock to a gate of each of the first transistor and the second transistor.
Claims20
A digital duty cycle corrector circuit, comprising:
- a control circuit comprising a first transistor and a second transistor, wherein:
- a drain/source of the first transistor is connected to a drain/source of the second transistor at a first node,
- a source/drain of the first transistor is connected to a first trim circuit, wherein the first trim circuit provides a first voltage at the source/drain of the first transistor
- a drain/source of the first transistor is connected to a drain/source of the second transistor at a first node,
- a source/drain of the second transistor is connected to a second trim circuit, wherein the second trim circuit provides a second voltage at the source/drain of the second transistor, wherein the second trim circuit comprises a second plurality of transistors, wherein each of the second plurality of transistors are connected in parallel to each other between the source/drain of the second transistor and a ground voltage node′
- the control circuit is configured to adjust a duty cycle of an input clock received at the first node and provide a duty adjusted output clock at a second node, and
- the control circuit further comprises a feedback circuit that connects the second node to a gate of each of the first transistor and the second transistor;
- and
- a single to differential circuit connected to the control circuit, wherein the single to differential circuit is configured to generate a first output clock and a second output clock from the duty adjusted output clock.
A digital duty cycle corrector circuit, comprising:
- a control circuit comprising a first transistor and a second transistor connected at a first node and configured to adjust a duty cycle of an input clock received at the first node and provide a duty adjusted output clock at a second node;
- a single to differential circuit connected to the control circuit at the second node, wherein the single to differential circuit is configured to generate a first output clock and a second output clock from the duty adjusted output clock;
- and
- a feedback circuit configured to provide the duty adjusting output clock to a gate of each of the first transistor and the second transistor, wherein the feedback circuit connects another node in another single to differential circuit that in a same phase as the second node to the gate of each of the first transistor and the second transistor.
A method of adjusting a duty cycle of an input clock, the method comprising:
- receiving an input clock at a first node of a control circuit comprising a first transistor and a second transistor connected at the first node;
- adjusting a duty cycle of the input clock based on a first trim code and a second trim code;
- providing a duty adjusted output clock at a second node of the control circuit;
- and
- providing the duty adjusted output clock as feedback at a gate of each of the first transistor and the second transistor of the control circuit, wherein the feedback circuit connects another node in the single to differential circuit that in a same phase as the second node to the gate of each of the first transistor and the second transistor.
Dependencies are inferred from the claim text.