Semiconductor system and method for operating the same

A semiconductor system, comprising:

• a duty cycle corrector (DCC) configured to receive an input clock signal, wherein the DCC is configured to adjust a duty cycle of the input clock signal and generate a first modified clock signal;
• and
• a digital quadrature error corrector (digital QEC) configured to receive the first modified clock signal, wherein the digital QEC is configured to adjust a delay of the first modified clock signal and generate a first output clock signal and a second output clock signal, wherein the digital QEC comprises:
• a first inverter chain comprising a plurality of inverters, configured to receive the first modified clock signal and generate the first output clock signal;
• a digital phase error detector (DPED) configured to receive the first output clock signal and perform XOR operation and XNOR operation on the first output clock signal to adjust a phase of the first output clock signal;
• and
• a finite state machine (FSM) electrically connected to the DPED and configured to receive the first output clock signal having the adjusted phase.

A method for operating a semiconductor system, comprising:

• receiving an input clock signal;
• adjusting a duty cycle of the input clock signal to generate a first modified clock signal;
• receiving the first modified clock signal;
• adjusting a delay of the first modified clock signal to generate a first output clock signal and a second output clock signal;
• delaying or advancing a quarter of period from the first output clock signal by the second output clock signal;
• receiving the first output clock signal and adjusting a phase of the first output clock signal;
• and
• filtering the first output clock signal having the adjusted phase.