Time interleaving circuit having glitch mitigation
AssigneeSTMicroelectronics International N.V.
InventorAradhana KUMARI
Life of this patent
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Abstract
Provided is a time interleaving circuit to mitigate glitches. A first loading stage outputs first data representative of first serialized data. A second loading stage generates second serialized data. The second loading stage receives the first data output by the first loading stage. In response to the first data having a first state, the time interleaving circuit inverts the second serialized data to generate second data representative of the second serialized data. In response to the first data having a second state, the time interleaving circuit outputting the second data without inverting the second serialized data. Exclusive disjunction logic receives the second data and operates on the first data and the second data to generate output data.
Claims20
A time interleaving circuit, comprising:
- a first loading stage configured receive first data and to output first serialized data from the first data, wherein the first loading stage is operated with a first clock signal;
- a second loading stage configured receive second data and to output serialized second data from the second data, wherein the second loading stage is operated with a second clock signal out of phase with the first clock signal;
- and
- an output stage configured to receive the first serialized data and the second serialized data and to generate serialized output data by serializing the first serialized output data and the second serialized output data.
A method, comprising:
- receiving a plurality of first data values in parallel at a first loading stage of a time interleaving circuit;
- controlling the first loading stage with a first clock signal;
- generating first serialized data by serializing the first data values with the first loading stage;
- receiving a plurality of second data values in parallel at a second loading stage of the time interleaving circuit;
- controlling the second loading stage with a second clock signal out of phase with the first clock signal;
- generating second serialized data by serializing the second data values with the second loading stage;
- and
- receiving the first serialized and the second serialized data with an output stage of the time interleaving circuit;
- and
- generating serialized output data by serializing the first and second serialized data with the output stage.
A system, comprising:
- a plurality of first data lines;
- a plurality of second data lines;
- a first loading stage coupled to the plurality of first data lines and configured to serialize parallel-loaded data of the plurality of first data lines into first serialized data;
- a second loading stage coupled to the plurality of second data lines and configured to serialize parallel-loaded data of the plurality of second data lines into second serialized data;
- exclusive disjunction logic configured to receive the first and second data and operate on the first data and the second data to generate output data.
Dependencies are inferred from the claim text.