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US 2026/0280538 A1Published application
Clock transmission device and operation method thereof
AssigneeMacronix International Co., Ltd.
InventorsTung-Yu Li, Shang-Chi Yang, Hsuan-Chieh Lin
Life of this patent
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Abstract
A clock transmission device and an operation method thereof are provided. The clock transmission device may be applied to a three-dimensional NAND flash memory with high capacity and high performance. The clock transmission device includes a clock transmission circuit and a jitter suppression circuit. The clock transmission circuit generates an output clock based on an input clock. The jitter suppression circuit supplies a power current to the clock transmission circuit based on a power voltage. The jitter suppression circuit adaptively adjusts the power current in response to a power supply noise of the power voltage to suppress the power noise induced jitter of the output clock.
Claims26
A clock transmission device comprising:
- a clock transmission circuit generating at least one output clock based on an input clock;
- and
- a jitter suppression circuit supplying a power current to the clock transmission circuit based on a power voltage,
- wherein the jitter suppression circuit adaptively adjusts the power current in response to a power supply noise of the power voltage to suppress a power noise induced jitter of the at least one output clock,
- wherein the jitter suppression circuit comprises:
- a noise amplification circuit sensing the power supply noise of the power voltage to generate a first control signal corresponding to the power supply noise;
- and
- a first compensation circuit, wherein an input end of the first compensation circuit receives the power voltage, an output end of the first compensation circuit is coupled to a power end of the clock transmission circuit to supply the power current, a control end of the first compensation circuit is coupled to the noise amplification circuit to receive the first control signal, and the first compensation circuit adaptively adjusts the power current in response to the first control signal,
- wherein the first compensation circuit comprises:
- a transistor, wherein a first end of the transistor receives the power voltage, a second end of the transistor is coupled to the power end of the clock transmission circuit to supply the power current, a control end of the transistor is coupled to the noise amplification circuit to receive the first control signal, and the transistor adaptively adjusts the power current in response to the first control signal;
- and
- a capacitor, wherein a first end of the capacitor receives the power voltage, and a second end of the capacitor is coupled to the control end of the transistor.
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A clock transmission device comprising:
- a clock transmission circuit generating at least one output clock based on an input clock;
- and
- a jitter suppression circuit supplying a power current to the clock transmission circuit based on a power voltage,
- wherein the jitter suppression circuit adaptively adjusts the power current in response to a power supply noise of the power voltage to suppress a power noise induced jitter of the at least one output clock,
- wherein the jitter suppression circuit comprises:
- a noise amplification circuit sensing the power supply noise of the power voltage to generate a first control signal corresponding to the power supply noise;
- and
- a first compensation circuit, wherein an input end of the first compensation circuit receives the power voltage, an output end of the first compensation circuit is coupled to a power end of the clock transmission circuit to supply the power current, a control end of the first compensation circuit is coupled to the noise amplification circuit to receive the first control signal, and the first compensation circuit adaptively adjusts the power current in response to the first control signal;
- wherein the noise amplification circuit comprises:
- an error amplification circuit, wherein a first input end of the error amplification circuit receives the power voltage, a second input end of the error amplification circuit receives a first reference voltage, and the error amplification circuit compares the power voltage with the first reference voltage to generate an error signal;
- and
- a gain circuit, wherein a first input end of the gain circuit is coupled to a first output end of the error amplification circuit, a second input end of the gain circuit is coupled to a second output end of the error amplification circuit, the gain circuit converts the error signal into the first control signal, and a first output end of the gain circuit is coupled to the control end of the first compensation circuit to supply the first control signal.
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An operation method of a clock transmission device, comprising:
- generating at least one output clock by a clock transmission circuit of the clock transmission device based on an input clock;
- supplying a power current to the clock transmission circuit by a jitter suppression circuit of the clock transmission device based on a power voltage;
- adaptively adjusting the power current by the jitter suppression circuit in response to a power supply noise of the power voltage, so as to suppress a power noise induced jitter of the at least one output clock;
- sensing the power supply noise of the power voltage to generate a first control signal corresponding to the power supply noise by a noise amplification circuit of the jitter suppression circuit:
- adaptively adjusting the power current in response to the first control signal by a first compensation circuit of the jitter suppression circuit, wherein an input end of the first compensation circuit receives the power voltage, an output end of the first compensation circuit is coupled to a power end of the clock transmission circuit to supply the power current, and a control end of the first compensation circuit is coupled to the noise amplification circuit to receive the first control signal;
- comparing the power voltage with a first reference voltage to generate an error signal by an error amplification circuit of the noise amplification circuit, wherein a first input end of the error amplification circuit receives the power voltage, and a second input end of the error amplification circuit receives the first reference voltage;
- and
- converting the error signal into the first control signal by a gain circuit of the noise amplification circuit, wherein a first input end of the gain circuit is coupled to a first output end of the error amplification circuit, a second input end of the gain circuit is coupled to a second output end of the error amplification circuit, and a first output end of the gain circuit is coupled to the control end of the first compensation circuit to supply the first control signal.
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Dependencies are inferred from the claim text.