Efficient pwm modulator utilizing interpolation
AssigneeAxign B.V.
InventorsJelmer Bas KOSTERS, Christiaan Egidius LOKIN, Daniel SCHINKEL
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Abstract
The present invention is in the field of basic electronic circuitry, in particular of a digital signal processor for streaming audio applications, more in particular a pulse-width modulator, an integrated circuit comprising said electronic circuit, and a device comprising said electronic circuitry or said integrated circuit, such as an audio device.
Claims18
Electronic circuit for pulse-width modulation comprising a clock generator configured to provide an operational clock speed for a coarse time grid, wherein the coarse time grid is provided to an input signal,
- a Digital pulse-width modulator, the DPWM configured to receive input, and configured to provide output to a Delay-line and to an Interpolator of an interpolation circuit,
- wherein the interpolation circuit-comprises
- a Delay-line configured to provide output to an edge selector, wherein the DL comprises a delay controller configured to control the delay of the DL, and configured to provide output to an edge selector,
- an Interpolator configured to receive input from the DPWM and from an error signal from the digital PWM modulator and to provide interpolated output to an edge selector, wherein the interpolator comprises a step-size detector configured to detect an increase in a carrier signal exceeding an input signal, and
- an edge selector configured to provide time quantized PWM output.
Delay-line for an electronic circuit, wherein the Delay-line is configured to pro-vide output to an edge selector, wherein the DL comprises a controller configured to control the delay of the DL and configured to provide output to the edge selector.
Pulse-width interpolator for an electronic circuit, wherein the interpolator is configured to provide interpolated output to the edge selector and to receive input from the Digital pulse-width modulator (DPWM) and from an error signal from the digital PWM modulator and to, comprising a step-size detector configured to detect an in-crease in a carrier signal exceeding an input signal, comprising a comparator configured for comparing the value of the carrier signal and the value of the input signal and providing an error signal, and a converter configured to convert the error signal into an integer value based on the number of quantized time grid elements and the error signal size and step-size
Dependencies are inferred from the claim text.