Memory systems and devices having enhanced column repair capability and methods of operating same

A method for operating a memory device, comprising:

• transmitting a first column address of a first memory cell stored in a fuse array to a first latch array of a first column repair circuit;
• outputting a first enable signal based on output bits of the first latch array, the first enable signal indicating whether to repair the first memory cell;
• comparing the output bits with a second column address and outputting a first address match signal based on a result of the comparing;
• and
• outputting a first column repair signal based on the first enable signal and the first address match signal.

A memory system, comprising:

• a memory controller configured to transmit an address of each of read data and write data to a memory device;
• and
• the memory device configured to repair a normal memory cell using a redundant memory cell,
• wherein the memory device includes:
• a memory cell array including a plurality of normal memory cells, and a plurality of redundant memory cells;
• a fuse array configured to store a first column address of a first memory cell;
• an address register configured to receive an address from the memory controller and output a second column address;
• and
• a column decoder configured to receive the first and second column addresses, wherein the column decoder comprises a first column repair circuit configured to output a first column repair signal based on a first enable signal and a first address match signal,
• wherein the first column repair circuit includes:
• a first latch array having a plurality of latch elements configured to receive the first column address and output first output bits,
• a first compare logic configured to receive the first output bits and a second column address and compare the second column address with the first output bits and output the first address match signal, and
• a first combinational logic configured to output the first enable signal based on the first output bits, the first enable signal indicating whether to repair the first memory cell.