Memory device and repair method of the memory device

A repair method of a memory device including a plurality of stacked physical layers and a plurality of cell regions, the repair method comprising:

• identifying whether a first bit line present in a first cell region or a second bit line present in a second cell region provided in a second physical layer different from a first physical layer of the first cell region is defective;
• and
• repairing the first bit line or the second bit line with a first redundant bit line or a second redundant bit line,
• wherein the repairing comprises:
• replacing the first bit line with the first redundant bit line based on the first bit line being identified as defective;
• and
• replacing the second bit line with the second redundant bit line based on the second bit line being identified as defective,
• wherein the first bit line and the second bit line are respectively connected to a plurality of first page buffers, and the first redundant bit line and the second redundant bit line are commonly connected to a second page buffer,
• wherein the first redundant bit line and the second redundant bit line share the second page buffer.

A memory device comprising:

• a first cell region provided in a first physical layer among a plurality of stacked physical layers of the memory device, the first cell region comprising a first bit line, a first redundant bit line, a first word line, and a first redundant word line;
• a second cell region provided in a second physical layer among the plurality of stacked physical layers, the second cell region comprising a second bit line, a second redundant bit line, a second word line, and a second redundant word line;
• a peripheral region provided in a third physical layer among the plurality of stacked physical layers, the peripheral region comprising:
• a plurality of first page buffers configured to be respectively connected to the first bit line and the second bit line;
• a second page buffer configured to be commonly connected to the first redundant bit line and the second redundant bit line;
• a plurality of first decoder circuits respectively connected to the first word line and the second word line;
• and a second decoder circuit commonly connected to the first redundant word line and the second redundant word line;
• and
• a control circuit configured to:
• based on the first bit line being identified as defective, replace the first bit line with the first redundant bit line;
• based on the second bit line being identified as defective, replace the second bit line with the second redundant bit line;
• based on the first word line being identified as defective, replace the first word line with the first redundant word line;
• and
• based on the second word line being identified as defective, replace the second word line with the second redundant word line,
• wherein the first redundant bit line and the second redundant bit line share the second page buffer.

A memory device comprising:

• a first cell region provided in a first physical layer among a plurality of stacked physical layers of the memory device, the first cell region comprising a first bit line and a first redundant bit line;
• a second cell region provided in a second physical layer among the plurality of stacked physical layers, the second cell region comprising a second bit line and a second redundant bit line, wherein the first cell region and the second cell region are connected to each other through a first bonding pad;
• and
• a peripheral region provided in a third physical layer among the plurality of stacked physical layers, the peripheral region comprising a plurality of first page buffers configured to be respectively connected to the first bit line and the second bit line, a second page buffer configured to be commonly connected to the first redundant bit line and the second redundant bit line, a plurality of pass transistors, and connected to the second cell region through a second bonding pad,
• wherein each of the plurality of pass transistors is shared by a first word line of the first cell region and a second word line of the second cell region corresponding to the first word line,
• wherein based on the first bit line being identified as defective, the first bit line is replaced with the first redundant bit line of the first cell region, and
• wherein based on the second bit line being identified as defective, the second bit line is replaced with the second redundant bit line of the second cell region.