Parallel operations in compute systems

A compute apparatus, comprising:

• a compute-in-memory (CIM) array comprising a plurality of memory cells including first storage elements and second storage elements;
• a first group of access lines coupled to the first storage elements and a second group of access lines coupled to the second storage elements;
• circuitry configured to write updated weight data into selected ones of the first storage elements or selected ones of the second storage elements based on an address signal and a selection signal;
• and
• compute circuitry configured to perform a vector-matrix multiplication operation using weight data output from storage elements that are not being written by the write circuitry,
• wherein the compute apparatus is configured to overlap a write operation for updating weight data in the first storage elements with the vector-matrix multiplication operation using weight data stored in the second storage elements.

A method of operating a compute-in-memory apparatus, the method comprising

• storing first weight data in first storage elements of memory cells of a compute-in-memory array;
• storing second weight data in second storage elements of the memory cells, the second weight data being different from the first weight data;
• receiving a selection signal that selects one of the first storage elements or the second storage elements for a weight update operation;
• writing updated weight data into the selected one of the first storage elements or the second storage elements using access lines addressed based on the selection signal and an address signal;
• and
• while writing the updated weight data, performing a vector-matrix multiplication operation using weight data stored in an unselected one of the first storage elements or the second storage elements.