Semiconductor memory device
AssigneeKioxia Corporation
InventorsKatsuaki SAKURAI, Hiroki IDE
Life of this patent
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Abstract
According to an embodiment, a semiconductor memory device includes a memory cell array including a memory cell, a word line coupled to the memory cell, a row decoder to which the word line is coupled, a first interconnect coupled to the row decoder, a voltage generator configured to execute charge and discharge of the word line via the first interconnect and the row decoder, a detection circuit included in the voltage generator and configured to output a first signal based on the discharge of the word line, and a determination circuit configured to determine whether the word line is nondefective or defective, based on the first signal.
Claims16
A semiconductor memory device comprising:
- a memory cell array including a memory cell;
- a word line coupled to the memory cell;
- a row decoder to which the word line is coupled;
- a first interconnect coupled to the row decoder;
- a voltage generator configured to execute charge and discharge of the word line via the first interconnect and the row decoder;
- a detection circuit included in the voltage generator and configured to output a first signal based on the discharge of the word line;
- and
- a determination circuit configured to determine whether the word line is nondefective or defective, based on the first signal.
Dependencies are inferred from the claim text.