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US 2026/0279472 A1Published application
Memory system
AssigneeKioxia Corporation
InventorKeita KIMURA
Life of this patent
Estimating the term…
Abstract
According to one embodiment, a memory system includes a semiconductor memory device and a control device. The control device instructs write operations and erase operations. In a write operation, write loops involving supplying a program voltage to a conductive layer are performed. The program voltage is increased for each subsequent write loop in the write operation. In an erase operation, a plurality of erase loops are performed, each including supplying an erase voltage then an erase verification operation. The semiconductor memory device outputs data corresponding to an erase verification operation result to the control device. Whenever executing a write operation, the control device transmits data indicating an initial program voltage to be used in the write operation based on the erase verification operation result.
Claims18
A memory system, comprising:
- a semiconductor memory device;
- and
- a control device connected to the semiconductor memory device, wherein
- the semiconductor memory device includes:
- a plurality of conductive layers spaced from each other in a first direction;
- a semiconductor pillar extending in the first direction in the plurality of conductive layers;
- a charge storage layer between the plurality of conductive layers and the semiconductor pillar;
- and
- a wiring electrically connected to one end of the semiconductor pillar,
- the control device is configured to:
- instruct a write operation and an erase operation of the semiconductor memory device,
- the write operation includes a plurality of write loops,
- each of the write loops includes a program operation of supplying a program voltage to a conductive layer of the plurality of conductive layers,
- the program voltage increases by an offset voltage from an initial program voltage as the number write loops increases in the write operation,
- the erase operation includes a plurality of erase loops,
- each of the erase loops includes:
- an erase voltage supply operation of supplying an erase voltage to the wiring;
- and
- an erase verification operation executed after the erase voltage supply operation is performed,
- the semiconductor memory device is configured to output first data corresponding to an execution result of the erase verification operation to the control device, and
- when executing the write operation, the control device refers to a table indicating a relationship between the first data and a magnitude to be used for the initial program voltage and transmits second data indicating the initial program voltage corresponding to the first data in the table to the semiconductor memory device.
18 more elements
A memory system, comprising:
- a semiconductor memory device;
- and
- a control device connected to the semiconductor memory device, wherein
- the semiconductor memory device includes:
- a plurality of conductive layers spaced from each other in a first direction;
- a semiconductor pillar extending in the first direction in the plurality of conductive layers;
- a charge storage layer between the plurality of conductive layers and the semiconductor pillar;
- and
- a wiring electrically connected to one end of the semiconductor pillar,
- the control device is configured to:
- instruct a write operation and an erase operation of the semiconductor memory device,
- the write operation includes a plurality of write loops,
- each of the write loops includes a program operation of supplying a program voltage to a conductive layer of the plurality of conductive layers,
- the program voltage increases by an offset voltage from an initial program voltage as the number of write loops increases in the write operation,
- the erase operation includes a plurality of erase loops,
- each of the erase loops includes:
- an erase voltage supply operation of supplying an erase voltage to the wiring;
- and
- an erase verification operation executed after the erase voltage supply operation is performed,
- the semiconductor memory device is configured to output the number of erase loops executed in the erase operation to the control device, and
- the control device is configured to adjust a magnitude of the initial program voltage in the write operation according to the output number of erase loops.
18 more elements
A memory system, comprising:
- a semiconductor memory device;
- and
- a control device connected to the semiconductor memory device, wherein
- the semiconductor memory device includes:
- a plurality of conductive layers spaced from each other in a first direction;
- a semiconductor pillar extending in the first direction in the plurality of conductive layers;
- a charge storage layer between the plurality of conductive layers and the semiconductor pillar;
- and
- a wiring electrically connected to one end of the semiconductor pillar,
- the control device is configured to:
- instruct a write operation and an erase operation of the semiconductor memory device,
- the write operation includes a plurality of write loops,
- each of the write loops includes a program operation of supplying a program voltage to a conductive layer of the plurality of conductive layers,
- the program voltage increases by an offset voltage from an initial program voltage as the number of write loops increases in the write operation,
- the erase operation includes a plurality of erase loops,
- each of the plurality of erase loops includes:
- an erase voltage supply operation of supplying an erase voltage to the wiring;
- and
- an erase verification operation executed after the erase voltage supply operation is performed,
- the semiconductor memory device is configured to output first data corresponding to an execution result of the erase verification operation to the control device, and
- the control device is configured to adjust an application time for the program voltage in the program operation in accordance with the first data.
18 more elements
Dependencies are inferred from the claim text.