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US 2026/0279470 A1Published application
Memory Circuit with Replica Column Multiplexer
OwnerLail Hajj-Ahmadinventor
Life of this patent
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Abstract
A system includes a memory circuit, which includes a bit cell array, a column multiplexer, and a current mirror circuit. The current mirror circuit includes compensating circuits to increase or reduce a bit cell programming current to achieve a desired value for the bit cell programming current, despite leakage current and bit cell process variation. The compensating circuits may include a replica column multiplexer and a splitting circuit.
Claims20
A circuit comprising:
- a first column multiplexer;
- a common bitline coupled to the first column multiplexer;
- a current mirror circuit coupled to the common bitline, wherein the current mirror circuit has:
- a first leg having:
- a current source;
- and
- a diode coupled between the current source and a power supply terminal;
- a second leg having a first transistor that has a control terminal coupled to a terminal of the diode, wherein a current path terminal of the first transistor is coupled to the first column multiplexer;
- and
- a second column multiplexer coupled to the diode.
7 more elements
A circuit comprising:
- a column multiplexer;
- a common bitline coupled to the column multiplexer;
- a current mirror circuit coupled to the common bitline, wherein the current mirror circuit has:
- a first leg having:
- a first current source;
- and
- a diode coupled between the first current source and a power supply terminal;
- and
- a second leg having a first transistor that has a control terminal coupled to a terminal of the diode, wherein a current path terminal of the first transistor is coupled to the column multiplexer;
- and
- a second current source;
- a second transistor having first and second current path terminals and a control terminal;
- and
- a third transistor having first and second current path terminals and a control terminal, wherein the first current path terminal of the second transistor is coupled to the second current source, the second current path terminal of the second transistor is coupled to the power supply terminal, and the control terminal of the second transistor is coupled to the second current path terminal of the third transistor, further wherein the first current path terminal of the third transistor is coupled to the second current source and the control terminal of the third transistor is coupled to the diode.
11 more elements
A circuit comprising:
- an array of bit cells, the array of bit cells having a plurality of columns;
- a column multiplexer, wherein each of the columns is coupled to the column multiplexer, wherein the column multiplexer has N pairs of transmission gates, each pair of transmission gates being coupled to a respective column and to a common bitline, wherein N is an integer greater than one;
- a current mirror circuit having a first leg and a second leg, wherein the second leg of the current mirror circuit is coupled to the common bitline;
- M pairs of transmission gates coupled to the first leg of the current mirror circuit, wherein M is an integer greater than one;
- a first transistor having first and second current path terminals and a control terminal;
- and
- a second transistor having first and second current path terminals and a control terminal, wherein the first current path terminal of the first transistor and the first current path terminal of the second transistor are coupled to a first current source, wherein the second current path terminal of the first transistor is coupled to a power supply terminal, wherein the second current path terminal of the second transistor is coupled to the common bitline, and wherein the control terminal of the second transistor is coupled to the first leg of the current mirror circuit.
4 more elements
Dependencies are inferred from the claim text.