Tracking scheme circuit of memory device and methods for operating the same

A memory device, comprising:

• a plurality of access word lines extending along a lateral direction and corresponding to a plurality of rows of a memory array, respectively;
• and
• a first tracking word line also extending along the lateral direction, and having a first portion and a second portion;
• wherein even-numbered ones of the plurality of access word lines each consist of two first conductor lines respectively disposed across a first combination of a plurality of metallization layers;
• wherein odd-numbered ones of the plurality of access word lines each consist of two second conductor lines respectively disposed across a second combination of the plurality of metallization layers;
• wherein the first portion of the first tracking word line consists of two third conductor lines respectively disposed across the first combination of the plurality of metallization layers, and the second portion of the first tracking word line consists of two fourth conductor lines respectively disposed across the second combination of the plurality of metallization layers;
• wherein the first combination is different from the second combination;
• and
• wherein the first combination includes a first one of the plurality of metallization layers that is a fifth closest to the memory array, and the second combination includes a third one of the plurality of metallization layers that is a third closest to the memory array.

A method for fabricating a memory device, comprising:

• forming, along a major surface of a substrate, a memory array including a plurality of bit cells arranged over a plurality of rows and a plurality of columns;
• forming a plurality of access word lines extending along a lateral direction and operatively coupled to the plurality of rows, respectively, wherein even-numbered ones of the plurality of access word lines each consist of two first conductor lines respectively disposed across a first combination of a plurality of metallization layers disposed above the major surface, and odd-numbered ones of the plurality of access word lines each consist of two second conductor lines respectively disposed across a second combination of the plurality of metallization layers;
• and
• forming a tracking word line also extending along the lateral direction, and having a first portion and a second portion;
• wherein the first portion of the tracking word line consists of two third conductor lines respectively disposed across the first combination of the plurality of metallization layers, and the second portion of the tracking word line consists of two fourth conductor lines respectively disposed across the second combination of the plurality of metallization layers;
• wherein the first combination is different from the second combination;
• and
• wherein the first combination includes a first one of the plurality of metallization layers that is a fifth closest to the memory array, and the second combination includes a third one of the plurality of metallization layers that is a third closest to the memory array.