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US 2026/0279433 A1Published application
Wafer-on-wafer formed memory and logic
AssigneeMicron Technology, Inc.
InventorsSean S. Eilert, Aliasger T. Zaidy, Glen E. Hush, Kunal R. Parekh
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Abstract
A wafer-on-wafer formed memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. The memory die can be formed as one of many memory dies on a first semiconductor wafer. The logic die can be formed as one of many logic dies on a second semiconductor wafer. The first and second wafers can be bonded via a wafer-on-wafer bonding process. The memory and logic device can be singulated from the bonded first and second wafers.
Claims11
An apparatus, comprising:
- a logic die comprising:
- logic circuitry configured to perform logical operations on data;
- and
- logic-to-memory circuitry coupled to the logic circuitry;
- and
- a memory die bonded to the logic die, the memory die comprising:
- memory-to-logic circuitry coupled to the logic-to-memory circuitry;
- an array of memory cells;
- a plurality of local input/output (LIO) lines coupled to the array of memory cells;
- a global input/output line coupled to the plurality of LIOs;
- and
- a respective transceiver coupled to each of the LIO lines, to the global input/output line, and to the memory-to-logic circuitry, wherein the respective transceiver is configured to provide:
- a first electrical connection between a corresponding LIO line and the global input/output line;
- and
- a second electrical connection between the corresponding LIO line and the memory-to-logic circuitry.
12 more elements
An apparatus, comprising
- a memory die, comprising:
- an array of memory cells;
- memory-to-logic circuitry coupled to the array of memory cells;
- and
- a plurality of local input/output (LIO) lines coupled to the array of memory cells;
- and
- a logic die bonded to the memory die, the logic die comprising:
- logic circuitry configured to perform logical operations on data;
- logic-to-memory circuitry coupled to the logic circuitry and to the memory-to-logic circuitry;
- and
- a respective transceiver coupled to the logic circuitry and to each of the LIO lines, wherein the respective transceiver is configured to cause signals indicative of data received at the logic die from a corresponding LIO to be provided to the logic circuitry.
8 more elements
Dependencies are inferred from the claim text.