Memory circuit and method of operating the same

A memory circuit, comprising:

• a memory macro comprising:
• a first memory cell array configured to store data;
• and
• an adder circuit reconfigurable as a first logic circuit or a second logic circuit in response to a first set of control signals, the first logic circuit being configured to perform a first logic function on a first set of data signals based on a second set of control signals, and the second logic circuit being configured to perform a second logic function on the first set of data signals based on the second set of control signals, the second logic function being different from the first logic function, the first set of data signals being part of the data stored in the first memory cell array;
• and
• a controller coupled to the memory macro, and being configured to generate the first set of control signals and configured to control the first memory cell array and the adder circuit,
• wherein the first memory cell array and the adder circuit are embedded in a same memory cell array.

A method of operating a memory circuit, the method comprising:

• initializing a first set of transistors, the first set of transistors being part of a first memory cell array in the memory circuit;
• writing a first set of control signals to the first set of transistors thereby setting a logic function of the first memory cell array in the memory circuit;
• performing a write operation of the first memory cell array;
• and
• performing a read operation of the memory circuit, the performing the read operation of the memory circuit comprising:
• setting a first node to a first supply voltage;
• pulling an output node to the first supply voltage or a reference supply voltage thereby setting an output signal;
• setting a first signal at the first node to the reference supply voltage;
• and
• outputting the output signal, the output signal corresponding to the logic function between a first data signal and a second data signal.