Low Power Scheme for Power Down in Integrated Dual Rail SRAMs
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorSanjeev Kumar JAIN
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Abstract
Systems and methods are provided for controlling power down of an integrated dual rail memory circuit. The power down system is configured to power down the power rail for input and logic components (VDD) while maintaining power to the power rail for the memory cells (VDDM). The power down system includes two voltage rails, a clock generator, and a power detector for detecting the power on VDD. The power detector generates an isolated power signal when voltage on VDD is below a voltage threshold. The isolated power signal is configured to disable the clock generator and thus reduce dynamic power as the read/write cycle is not triggered during power down.
Claims20
A circuit comprising:
- a power detector configured to generate a power signal responsive to a voltage on a first voltage rail;
- first circuitry configured to provide a shifted clock signal;
- and
- second circuitry configured to generate an enabling signal to disable a clock generator based on the power signal and the shifted clock signal.
A method comprising:
- powering down a first voltage rail by disabling a clock generator while a second voltage rail remains powered on, wherein each of the first and second voltage rails has a voltage level higher than a ground voltage.
A circuit comprising:
- first circuitry configured to generate a shifted clock signal;
- and
- second circuitry configured to generate an enabling signal to disable a clock generator based on a voltage on a first power rail and the shifted clock signal.
Dependencies are inferred from the claim text.