Automatic layout based pattern recognition search

A method of identifying alignment areas for the examination of semiconductor specimens, the method comprising:

• obtaining a layout file specifying a layout of a semiconductor element;
• generating a candidate set comprising a plurality of candidate areas for aligning an examination tool to image a specimen of said semiconductor element at a desired location by performing a polygon density analysis to identify areas within at least a portion of said layout having a polygon density within a specified density range;
• filtering said candidate set by sequentially performing:
• removing candidate areas that are outside a specified distance range from said desired location from said candidate set;
• and
• removing candidate areas that lack features with vertices within said candidate area from said candidate set;
• and
• providing said filtered candidate set for use by an examination tool for a semiconductor element.

A non-transitory computer readable storage medium tangibly embodying a program of instructions that, when executed by a computer, cause the computer to perform a method of identifying alignment areas for the examination of semiconductor specimens, said method comprising:

• generating a candidate set comprising a plurality of candidate areas for aligning an examination tool to image a specimen of said semiconductor element at a desired location by performing a polygon density analysis to identify areas having a polygon density within a specified density range within at least a portion of a layout of a semiconductor element;
• filtering said candidate set by sequentially performing:
• removing candidate areas that are outside a specified distance range from said desired location from said candidate set;
• and
• removing candidate areas that lack features with vertices within said candidate area from said candidate set;
• and
• providing said filtered candidate set for use by an examination tool for a semiconductor element.