Systems and Methods for Construction and Implementation of Efficient Feature Extractors

An application-specific integrated circuit (ASIC), comprising:

• input circuitry configured to receive an inference input and to form a feature extractor input vector therefrom;
• feature extraction circuitry configured to compute one or more activation values according to a quantized feature direction and at least one further quantized feature direction embodied in the ASIC;
• and
• feature output circuitry configured to generate one or more feature outputs from the one or more activation values, wherein the ASIC is manufactured based on data representing the quantized feature direction and the at least one further quantized feature direction, the data being produced by a process comprising:
• determining, from a dataset, a feature direction, wherein the feature direction is a vector or a tensor and comprises at least two components;
• quantizing the feature direction to produce a quantized feature direction;
• modifying the dataset by removing therefrom a contribution corresponding to the quantized feature direction, rather than removing therefrom a contribution corresponding to the feature direction prior to quantization, thereby producing a modified dataset that retains residual error introduced by the quantization;
• iteratively repeating the determining, quantizing, and modifying to produce at least one further quantized feature direction, each further quantized feature direction being determined from a corresponding modified dataset from which contributions of previously produced quantized feature directions have been removed;
• and
• outputting data representing the quantized feature direction and the at least one further quantized feature direction for synthesis into hardware.

A computer-implemented method for constructing a shared hardware implementation of a plurality of feature extractors, each feature extractor defined by coefficients over a common set of input signal dimensions or over respective overlapping sets of input signal dimensions, the method comprising:

• identifying, across the plurality of feature extractors, a selected multi-element tuple of input signal dimensions that satisfies a sharing criterion for a plurality of the feature extractors, the sharing criterion comprising at least one criterion selected from a set of criteria that includes:
• (i) respective feature extractors assigning identical nonzero coefficient values to the input signal dimensions of the multi-element tuple, and (ii) respective feature extractors assigning proportional nonzero coefficient values to the input signal dimensions of the selected multi-element tuple;
• creating a merged channel representing a sum or weighted sum of the input signal dimensions of the selected multi-element tuple;
• modifying, for at least some of the feature extractors that satisfy the sharing criterion for the selected multi-element tuple, the at least some feature extractors by replacing references to the selected multi-element tuple with a reference to the merged channel and adjusting one or more coefficients to account for the replacement;
• iteratively repeating the identifying, creating, and modifying using a modified set of feature extractors, including previously created merged channels as candidates for further merging;
• and
• outputting data representing the modified set of feature extractors and the merged channels for synthesis into shared hardware,
• wherein each merged channel corresponds to a shared arithmetic unit whose output is routed to two or more feature extractors that reference the merged channel, thereby reducing a total number of arithmetic operations relative to independent implementation of the plurality of feature extractors.