Interconnect method for memory expansion, scale-up and scale-out of ai/ml systems

An interconnect system for a plurality of processors provided on M racks, the interconnect system comprising:

• a plurality of scale-out switches, each scale-out switch having a first interface coupled to an I/O interface of one of the plurality of processors and N second interfaces providing selective connectivity to N planes of inter-rack switching;
• and
• an inter-rack switch cluster comprising the N planes of inter-rack switching, each plane comprising a plurality of inter-rack switches, each inter-rack switch comprising M first interfaces and M second interfaces each coupled to a scale-out switch of a processor on a respective one of the M racks.

A method for establishing a connection between a first processor provided on a first rack and a second processor provided on a second rack via an inter-rack switch cluster comprising N planes of inter-rack switching, the method comprising:

• operating an inter-rack switch in one of the N planes to preestablish a connection path between the first processor and the second processor;
• and
• once the connection path has stabilized, operating a scale-out switch coupled to the first processor to connect the first processor to the connection path in the one of the N planes.