US 2026/0277833 A1 · Memory and Storage Control Coordination

Abstract

Moving large amounts of data from persistent storage to volatile memory involves significant data routing overhead that increases latency and consumes battery power. If an electronic device transitions to a deep sleep state to save power, restoring the system state data upon awakening is a slow process that negatively impacts device responsiveness. This document describes hardware and techniques that enable memory and storage control coordination. To accelerate data transfers, a local interconnect couples a storage controller to a memory controller. This arrangement allows the storage controller to bypass a coherent interconnect when sending data to the memory controller. By bypassing the coherent interconnect, the electronic device can avoid packetizing data into flits. Consequently, data transfer latency is reduced, enabling the electronic device to transition into aggressive power-saving states to extend battery life in a wider variety of scenarios.

Claims20

Dependent claims

An apparatus comprising:

a coherent interconnect;
at least one processor coupled to the coherent interconnect;
a local interconnect;
a memory controller coupled to the coherent interconnect and the local interconnect, the memory controller configured to communicate with the at least one processor using the coherent interconnect;
and
a storage controller coupled to the local interconnect, the storage controller configured to bypass the coherent interconnect by communicating with the memory controller using the local interconnect.

3 more elements

Dependencies are inferred from the claim text.

Memory and Storage Control Coordination

Life of this patent

Memory and Storage Control Coordination

Life of this patent

Abstract

Claims20