Arbitrated shared instruction memory
AssigneeMicron Technology, Inc.
InventorLeon Zlotnik
Life of this patent
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Abstract
The present disclosure introduces a system for managing access to shared instruction memory in multi-processor environments, utilizing advanced arbitration and flow control strategies. The system may include a controller with a collision manager that dynamically prioritizes access requests based on timing requirements and urgency, reducing latency and optimizing memory access patterns. In some examples, it incorporates mechanisms for handling overlapping, prioritized, protected, exclusive, and atomic addresses, enhancing efficiency and resource utilization. Additionally, a common cache and multi-cache controller may be used to facilitate seamless integration and synchronization between processors and system components, improving performance and power efficiency over traditional methods.
Claims20
A method, comprising:
- at a memory system, using a hardware processor:
- receiving, from a first processing unit, a first access request to access a first instruction from a first address of a memory;
- receiving, from a second processing unit, a second access request to access a second instruction from a second address of the memory;
- determining a priority level associated with the first processing unit is higher than a priority level associated with the second processing unit;
- responsive to determining the priority level associated with the first processing unit is higher, retrieving the first instruction from the first address of the memory before retrieving the second instruction from the second address of the memory;
- providing the first instruction to the first processing unit within a timing requirement associated with the first processing unit;
- and
- providing, to the second processing unit, an alternative instruction instead of the second instruction responsive to determining the second instruction cannot be provided within a timing requirement associated with the second processing unit, wherein the alternative instruction, when executed by the second processing unit, causes the second processing unit to subsequently request the second instruction from the second address of the memory.
A non-transitory machine-readable medium, storing instructions for managing access to shared instruction memory, the instructions, which when executed, cause the machine to perform operations comprising:
- receiving, from a first processing unit, a first access request to access a first instruction from a first address of a memory;
- receiving, from a second processing unit, a second access request to access a second instruction from a second address of the memory;
- determining a priority level associated with the first processing unit is higher than a priority level associated with the second processing unit;
- responsive to determining the priority level associated with the first processing unit is higher, retrieving the first instruction from the first address of the memory before retrieving the second instruction from the second address of the memory;
- providing the first instruction to the first processing unit within a timing requirement associated with the first processing unit;
- and
- providing, to the second processing unit, an alternative instruction instead of the second instruction responsive to determining the second instruction cannot be provided within a timing requirement associated with the second processing unit, wherein the alternative instruction, when executed by the second processing unit, causes the second processing unit to subsequently request the second instruction from the second address of the memory.
A computing device for managing access to shared instruction memory, the computing device comprising:
- a hardware processor;
- a memory, the memory storing instructions, which when executed by the hardware processor cause the computing device to perform operations comprising:
- receiving, from a first processing unit, a first access request to access a first instruction from a first address of a memory;
- receiving, from a second processing unit, a second access request to access a second instruction from a second address of the memory;
- determining a priority level associated with the first processing unit is higher than a priority level associated with the second processing unit;
- responsive to determining the priority level associated with the first processing unit is higher, retrieving the first instruction from the first address of the memory before retrieving the second instruction from the second address of the memory;
- providing the first instruction to the first processing unit within a timing requirement associated with the first processing unit;
- and
- providing, to the second processing unit, an alternative instruction instead of the second instruction responsive to determining the second instruction cannot be provided within a timing requirement associated with the second processing unit, wherein the alternative instruction, when executed by the second processing unit, causes the second processing unit to subsequently request the second instruction from the second address of the memory.
Dependencies are inferred from the claim text.