Storage and access of data and tags in a multi-way set associative cache

A stacked dynamic random access memory (DRAM) device comprising:

• a plurality of DRAM layers, each DRAM layer comprising a plurality of data rows and a plurality of tag rows;
• a base layer vertically coupled to the plurality of DRAM layers, the base layer comprising:
• a communication interface to receive a first group of address bits;
• and
• one or more comparators configured to:
• generate a tag match indication and one or more set bits based on the first group of address bits and a first group of tag information bits from the plurality of tag rows;
• and
• combine, based on the tag match indication, the one or more set bits and the first group of address bits to generate a second group of address bits.

A stacked dynamic random access memory (DRAM) device comprising:

• one or more DRAM layers, each DRAM layer comprising one or more banks, each bank comprising a plurality of mats, each mat comprising a plurality of DRAM cells in rows and columns;
• a majority of the rows comprising rows for data as data rows, a minority of the rows comprising rows for tags, as tag rows;
• and
• a base layer vertically coupled to the one or more DRAM layers, the base layer comprising:
• a communication interface to receive a first group of address bits;
• and
• one or more comparators each to:
• generate a tag match indication and one or more set bits based on the first group of address bits and a first group of tag information bits from the tag rows;
• and
• combine, based on the tag match indication, the one or more set bits and the first group of address bits to generate a second group of address bits.

A method of operating a stacked dynamic random access memory (DRAM) device, comprising:

• presenting a first group of address bits to each of one or more comparators in a base layer vertically coupled to one or more DRAM layers, wherein each of the one or more DRAM layers has data rows and tag rows;
• generating a tag match indication and one or more set bits based on the first group of address bits and a first group of tag information bits from the tag rows;
• and
• combining, based on the tag match indication, the one or more set bits and the first group of address bits to generate a second group of address bits.