I/O Agent

A system, comprising:

• a first memory controller circuit configured to couple to a memory and manage access to data stored in the memory;
• a processor circuit configured to retrieve instructions from the memory via the first memory controller circuit and execute the instructions;
• an interconnect configured to couple the first memory controller circuit to the processor circuit;
• one or more peripheral components configured to issue read requests associated with the memory;
• and
• an input/output (I/O) agent circuit coupled to the one or more peripheral components and the interconnect, wherein the I/O agent circuit is configured to:
• implement coherency mechanisms to bridge the one or more peripheral components to the interconnect so that the one or more peripheral components can interact with circuitry coupled to the interconnect, including the first memory controller circuit;
• receive a first read request from a particular one of the one or more peripheral components;
• issue, to the first memory controller circuit, a request for exclusive ownership of a cache line;
• process, after obtaining the exclusive ownership of the cache line, the first read request with respect to data of the cache line;
• and
• release the exclusive ownership of the cache line without having performed a write to the cache line while the exclusive ownership was held.

A system, comprising:

• a memory controller circuit configured to manage access to data stored in a memory;
• one or more peripheral components configured to issue write requests associated with the memory;
• and
• an input/output (I/O) agent circuit that is configured to bridge the one or more peripheral components to the memory controller circuit via an interconnect, wherein the I/O agent circuit includes a first cache and a second cache, and wherein the I/O agent circuit is configured to:
• receive a first write request from a particular one of the one or more peripheral components;
• issue, to the memory controller circuit, a request for exclusive ownership of a cache line;
• receive first data of the cache line;
• store the first data of the cache line in the first cache of the I/O agent circuit;
• store second data of the first write request in the second cache of the I/O agent circuit;
• and
• merge the first data of the cache line with the second data of the first write request such that a first portion of the cache line is updated but a second portion of the cache line is unchanged.

A system, comprising:

• a memory controller circuit configured to manage access to data stored in a memory;
• one or more peripheral components configured to issue write requests associated with the memory;
• and
• an input/output (I/O) agent circuit that is configured to bridge the one or more peripheral components to the memory controller circuit via an interconnect, wherein the I/O agent circuit is configured to:
• implement coherency mechanisms so that the one or more peripheral components can interact with the memory controller circuit;
• and
• issue, to the memory controller circuit that is configured to manage access to data corresponding to a cache line of a plurality of cache lines, a request for exclusive ownership of the cache line without receiving the corresponding data for the cache line if (1) the I/O agent circuit is to perform a full write to the cache line and (2) the cache line is not in a modified state.