US 2026/0277788 A1 · MEMORY SYSTEM AND METHOD

Abstract

According to one embodiment, a memory system includes first memories operable in parallel and a memory controller. The memory controller manages multiple groups each including some of the first memories. The multiple groups include a first group and a second group. The memory controller causes each of the first memories to perform a first erase operation such that the some of the first memories included in each of the multiple groups are caused to perform the first erase operation at timing different among the multiple groups. The memory controller causes one or more of the first memories included in the second group to perform a program operation or a sense operation while the first erase operation is being performed in each of the some of the first memories included in the first group.

Claims20

Dependent claims

A memory system comprising:

a first number of first memories operable in parallel, the first number being an integer of 2 or larger;
and
a memory controller configured to:
manage a plurality of groups each including a second number of the first memories, the second number being an integer not smaller than 1 and smaller than the first number, the plurality of groups including at least a first group and a second group;
cause each of the first number of the first memories to perform a first erase operation such that the second number of the first memories included in each of the plurality of groups are caused to perform the first erase operation at timing different among the plurality of groups;
and
cause one or more of the first memories included in the second group to perform a program operation or a sense operation while the first erase operation is being performed in each of the second number of the first memories included in the first group.

4 more elements

A method of controlling a first number of first memories operable in parallel, the first number being an integer of 2 or larger, the method comprising:

managing a plurality of groups each including a second number of the first memories, the second number being an integer not smaller than 1 and smaller than the first number, the plurality of groups including at least a first group and a second group;
causing each of the first number of the first memories to perform a first erase operation such that the second number of the first memories included in each of the plurality of groups are caused to perform the first erase operation at timing different among the plurality of groups;
and
causing one or more of the first memories included in the second group to perform a program operation or a sense operation while the first erase operation is being performed in each of the second number of the first memories included in the first group.

1 more element

Dependencies are inferred from the claim text.

Memory system and method

Life of this patent

Memory system and method

Life of this patent

Abstract

Claims20