Fault aggregation and remapping in an electronic system

A network-on-chip (NoC) comprising:

• a transport interconnect;
• a plurality of network interface units (NIUs) connected to the transport interconnect;
• and
• a fault aggregation circuit including:
• a plurality of input fault aggregators, wherein the NIUs provide faults to the input fault aggregators and wherein each input fault aggregator aggregates and remaps the faults to a few alarm levels;
• and
• an output fault aggregator having inputs operatively coupled to outputs of the input fault aggregators, the output fault aggregated configured to aggregate alarms from the plurality of input fault aggregators and output the few alarm levels.

A circuit for aggregating and remapping faults generated by an electronic system, the circuit comprising:

• a plurality of fault aggregators at an input stage;
• and
• a fault aggregator at an upstream stage,
• wherein each of the fault aggregators at the input stage has a number of fault inputs and logic for remapping faults at the fault inputs into a few alarm levels, and
• wherein the fault aggregator at the upstream stage consolidates the few alarm levels from the plurality of fault aggregators at the input stage into the few alarm levels.