Error tracking by a memory system
AssigneeMicron Technology, Inc.
InventorSai Krishna Mylavarapu
Life of this patent
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Abstract
Methods, systems, and devices for error tracking by a memory system are described. A memory system transmit indications of corrupt data without storing (e.g., internally storing) the indication. In some examples, a memory system may read data (e.g., from an associated memory device) and detect an error in the data. The memory system may generate an indication of the error and may transmit the indication to a host device. In other examples, a host device may transmit corrupted data with an indication of such. The memory system may store the corrupt data (e.g., an inverted version of the corrupt data) and, upon receiving a subsequent read command, may transmit the corrupt data to the host system with an indication that the data is corrupt.
Claims20
A method, comprising:
- receiving a command that comprises a plurality of bits, wherein at least a first bit of the plurality of bits indicates a validity of a first set of data;
- inverting, a subset of the plurality of bits to generate a second set of data based on at least the first bit indicating that the first set of data is invalid;
- and
- transmitting a third set of data that comprises the second set of data and a second bit indicating a validity of the second set of data based on inverting the subset of the plurality of bits.
A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to:
- receive a command that comprises a plurality of bits, wherein at least a first bit of the plurality of bits indicates a validity of a first set of data;
- inverting, a subset of the plurality of bits to generate a second set of data based on at least the first bit indicating that the first set of data is invalid;
- and
- transmit a third set of data that comprises the second set of data and a second bit indicating a validity of the second set of data based on inverting the subset of the plurality of bits.
An apparatus, comprising:
- a controller associated with a memory device, wherein the controller is configured to cause the apparatus to:
- receive a command that comprises a plurality of bits, wherein at least a first bit of the plurality of bits indicates a validity of a first set of data;
- inverting, a subset of the plurality of bits to generate a second set of data based on at least the first bit indicating that the first set of data is invalid;
- and
- transmit a third set of data that comprises the second set of data and a second bit indicating a validity of the second set of data based on inverting the subset of the plurality of bits.
Dependencies are inferred from the claim text.