Scheduling Tasks Using Work Fullness Counter

An apparatus comprising:

• hardware logic arranged to check if a flag for a decoded instruction is set in a scheduled task in an active state is set;
• hardware logic arranged, in response to determining that the flag is set, to check if a pipeline targeted by the decoded instruction is full, and in response to determining that the targeted pipeline is full, to cause a scheduled task to be de-activated;
• and
• hardware logic arranged, in response to determining that the flag is not set, to send the decoded instruction to the targeted pipeline for execution.

A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an apparatus comprising:

• hardware logic arranged to check if a flag for a decoded instruction in a scheduled task in an active state is set;
• hardware logic arranged, in response to determining that the flag is set, to check if a pipeline targeted by the decoded instruction is full, and in response to determining that the targeted pipeline is full, cause a scheduled task to be de-activated;
• and
• hardware logic arranged, in response to determining that the flag is not set, to send the decoded instruction to the targeted pipeline for execution.