US 2026/0277548 A1 · DATAFLOW ARCHITECTURE FOR HIGH-PERFORMANCE ASICS

Abstract

The present disclosure relates to an integrated circuit system for dataflow management. The system includes multiple compute cores and an interconnect structure that couples the compute cores together. Each compute core can include one or more register files configured to store operand data, an algorithm-logic unit (ALU) coupled to the register files to perform operations based on the operand data, and an input/output unit (IOU) coupled to the register files and the ALU. The interconnect structure can include multiple addressable pipeline registers disposed between different compute cores. At least one addressable pipeline register can be coupled to one or more register files in a compute core through the IOU of the respective compute core. In this system, data from the addressable pipeline register can be provided directly to the register files of that compute core as operand data without relying on a typical memory as the transfer medium.

Claims22

Dependent claims

An integrated circuit system for dataflow management, the system comprising:

a plurality of compute cores, wherein each of the compute cores includes:
one or more register files configured to store operand data;
an algorithm-logic unit (ALU) coupled to the one or more register files and configured to perform operations based on the operand data in the one or more register files;
and
an input/output unit (IOU) coupled to the one or more register files and the ALU;
and
an interconnect structure configured to couple the plurality of compute cores through the IOU of the respective compute core, the interconnect structure comprising a plurality of addressable pipeline registers disposed between different compute cores of the plurality of compute cores, wherein:
at least one of the plurality of addressable pipeline registers is coupled directly to the one or more register files in a compute core of the plurality of compute cores through the input/output unit of the respective compute core.

5 more elements

A method for dataflow management, the method being performed by a computing system having a plurality of compute cores and an interconnect structure having a plurality of addressable pipeline registers (APRs), the method comprising:

receiving, at an input/output unit (IOU) included in a destination compute core of the plurality of compute cores, a capsule code comprising one or more tensor identifiers and one or more instructions;
transferring tensor data from one or more source APRs of the plurality of APRs toward a destination APR of the plurality of APRs, the destination APR being coupled with the destination compute core;
receiving, at the IOU of the destination compute core, the tensor data directly from the destination APR;
executing, by an algorithm-logic unit (ALU) of the destination compute core, the one or more instructions of the capsule code in response to operand data being available at one or more register files (RFs) included in the destination compute core, wherein the one or more RFs have a higher data transfer bandwidth than memory.

1 more element

Dependencies are inferred from the claim text.

Dataflow architecture for high-performance asics

Life of this patent

Dataflow architecture for high-performance asics

Life of this patent

Abstract

Claims22