Memory device and computing device

A memory device comprising:

• a memory cell array including memory cells connected to word lines and bit lines, the memory cells being NAND flash memory cells;
• a plurality of page buffers configured to, in a deep neural network computing operation, store first values read from first memory cells connected to a first word line among the word lines through the bit lines and further configured to respectively perform multiplication operations on inputs and the first values;
• and
• a plurality of majority check circuits respectively connected to a plurality of page buffer groups into which the plurality of page buffers are divided,
• wherein each of the plurality of majority check circuits is configured to, in the deep neural network computing operation, perform a majority check operation on multiplication results received from one or more corresponding page buffers included in a corresponding page buffer group and output a final multiplication result.

A computing device comprising:

• a memory device including memory cells connected to word lines and bit lines, the memory cells being NAND flash memory cells and including first memory cells connected to a first word line among the word lines, the first memory cells storing first parameters corresponding to input connections of nodes of a first hidden layer of a deep neural network;
• and
• a controller configured to control the memory device to perform a deep neural network computing operation by transmitting external inputs to the memory device,
• wherein the memory device further comprises a plurality of page buffers configured to, in the deep neural network computing operation, respectively store the first parameters read from the first memory cells through the bit lines, respectively store the external inputs, and respectively perform multiplication operations on the external inputs and the first parameters.