Static power reduction in caches using deterministic naps
AssigneeTexas Instruments Incorporated
InventorsOluleye Olorode, Mehrdad Nourani
Life of this patent
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Abstract
Disclosed embodiments relate to a dNap architecture that accurately transitions cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.
Claims20
A method comprising:
- receiving a memory access request;
- decoding an address associated with the memory access request;
- determining a first subset of cache lines in a memory to which the memory access request is directed based on the decoded address;
- transitioning the first subset of cache lines from a low power state to an operating state;
- determining that the memory access request is associated with a hit in a second subset of cache lines in the memory, the second subset of cache lines included in, and less than, the first subset of the cache lines;
- and
- in response to determining that the memory access request is associated with a hit in the second subset of cache lines, transitioning a third subset of cache lines from the operating state to the low power state, the third subset of cache lines including cache lines that are not included in the second subset of the cache lines.
A memory system comprising:
- a data memory including sets of cache lines, each set of cache lines extending across multiple ways;
- and
- processing circuitry configured to receive cache access requests and control power states of the cache lines of the sets of cache lines, in which in response to a first cache access request, the processing circuitry is configured to:
- transition a first group of cache lines to which the first cache access request is directed from a low power state to an operating power state, the first group of cache lines including a plurality of sets of cache lines across the multiple ways;
- determine a single way of the multiple ways to which the cache access request is directed;
- transition cache lines in the first group of cache lines not in the single way from the operating power state to the low power state;
- and
- access one or more cache lines in the single way to which the first cache access request is directed.
Dependencies are inferred from the claim text.