Voltage droop detection and mitigation circuit sharing delay line, and clock supply circuit including the same

A clock supply circuit comprising:

• a clock signal output circuit configured to, based on a flag signal having a first value, output an input clock signal that has passed through a delay line, to which voltage is supplied from a supply voltage line, as a first clock signal;
• and
• a droop detection circuit configured to detect a droop in the voltage based on a propagation degree of the first clock signal in the delay line, and to convert the flag signal to a second value,
• wherein the clock signal output circuit is further configured to, based on the flag signal having the second value, output a second clock signal generated using the delay line.

A clock supply circuit comprising:

• a clock signal output circuit configured to:
• based on a flag signal having a first value, output an input clock signal that has passed through a delay line, to which a voltage is supplied from a supply voltage line, as a first clock signal, and
• based on the flag signal having a second value, output a second clock signal generated using the delay line, wherein the first clock signal has a first frequency and the second clock signal has a second frequency;
• and
• a droop mitigation circuit configured to output an output selection signal for the delay line to the clock signal output circuit to control the second frequency of the second clock signal to reach a target frequency,
• wherein the first value indicates non-detection of a droop of the voltage,
• wherein the second value indicates detection of the droop of the voltage, and
• wherein the droop mitigation circuit is further configured to switch the flag signal from the second value to the first value based on a phase difference between the input clock signal and the second clock signal having the target frequency being less than a second threshold.