Glitch-free reset testing system

A reset generation logic circuit, comprising:

• a functional combinational logic circuit configured to process reset signals during functional operation;
• a first OR gate having a first input coupled to receive a one-hot decoder reset signal and a second input coupled to receive a scan reset signal;
• an AND gate having a first input coupled to an output of the first OR gate and a second input coupled to receive a scan mode control signal;
• and
• a second OR gate having a first input coupled to an output of the AND gate and a second input coupled to an output of the functional combinational logic circuit, the second OR gate configured to selectively output the functional reset signal or the test reset signal based on the scan mode control signal,
• wherein the one-hot decoder reset signal is derived from a one-hot decoder that controls reset distribution to prevent glitch propagation by activating reset in one stage at a time.

A method for design for testability (DFT) in a system-on-chip (SoC), the method comprising:

• loading test values into one-hot decoders within a reset generation circuit, a reset select logic circuit, and a plurality of intellectual property (IP) blocks during a shift phase in response to a scan enable signal being at a first logic level, wherein the reset generation circuit is configured to generate reset signals, the reset select logic circuit is configured to route reset signals, and each IP block is configured to perform dedicated processing operations within the system-on-chip;
• transitioning the scan enable signal to a second logic level to begin a capture phase;
• transitioning a scan reset signal from the first logic level to the second logic level during the capture phase;
• and
• controlling reset distribution based on values in the one-hot decoders to prevent glitch propagation by activating reset in one stage at a time.