Semiconductor device and method of manufacturing the same
AssigneeSamsung Electronics Co., Ltd.
InventorsMingyu Kim, Jinwoo Han
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a memory cell structure and a peripheral circuit structure arranged on the memory cell structure. The peripheral circuit structure includes a first substrate including at least one substrate region doped with impurities, a peripheral circuit transistor arranged on the at least one substrate region, a peripheral circuit wire layer electrically connected to the peripheral circuit transistor, a passivation layer arranged on the at least one substrate region, and a trench isolation layer penetrating the at least one substrate region, and the passivation layer exposes the trench isolation layer.
Claims20
A semiconductor device comprising:
- a memory cell structure;
- and
- a peripheral circuit structure on the memory cell structure,
- wherein the peripheral circuit structure comprises
- a first substrate comprising at least one substrate region doped with impurities,
- a peripheral circuit transistor on the at least one substrate region,
- a peripheral circuit wire layer electrically connected to the peripheral circuit transistor,
- a passivation layer on the at least one substrate region, and
- a trench isolation layer extending into the at least one substrate region, and
- wherein the passivation layer exposes the trench isolation layer.
A semiconductor device comprising:
- a memory cell structure;
- a peripheral circuit structure on the memory cell structure;
- and
- a through via electrically connecting the memory cell structure to the peripheral circuit structure,
- wherein the peripheral circuit structure comprises
- a first substrate comprising at least one substrate region doped with impurities,
- a peripheral circuit transistor on the at least one substrate region,
- a peripheral circuit wire layer electrically connected to the peripheral circuit transistor, and
- a passivation layer on the at least one substrate region,
- wherein the through via extends into a trench isolation layer, wherein the trench isolation layer extends into the at least one substrate region in a vertical direction, and
- wherein the passivation layer exposes the trench isolation layer.
A semiconductor device comprising:
- a memory cell structure;
- a peripheral circuit structure on the memory cell structure;
- and
- a through via electrically connecting the memory cell structure to the peripheral circuit structure,
- wherein the peripheral circuit structure comprises
- a first substrate comprising a first substrate region and a second substrate region that have different conductivity types,
- a peripheral circuit transistor on each of the first substrate region and the second substrate region,
- a peripheral circuit wire layer electrically connected to the peripheral circuit transistor, and
- a passivation layer on the first substrate region,
- wherein the through via extends into a trench isolation layer that extends into the second substrate region and extends in a vertical direction,
- wherein the memory cell structure comprises
- a second substrate,
- a stack structure on the second substrate, the stack structure comprising a plurality of insulating layers and a plurality of conductive lines that are alternately stacked,
- a plurality of channel regions spaced apart from each other in a vertical direction,
- a gate insulating layer between respective ones of the plurality of channel regions and the plurality of conductive lines, and
- a cell wire layer electrically connected to an uppermost conductive line among the plurality of conductive lines, and
- wherein the passivation layer is configured to expose at least a portion of the trench isolation layer and the second substrate region.
Dependencies are inferred from the claim text.