Semiconductor package

A semiconductor package comprising:

• a substrate including first and second bonding pads;
• at least two chip structures disposed on the substrate and spaced apart from each other in a first direction;
• at least one controller disposed between the at least two chip structures, the at least one controller including edge pads arranged in at least two columns in a second direction, perpendicular to the first direction, and center pads arranged in at least one column in the second direction between the edge pads on opposite sides;
• a first bonding wire structure connecting the edge pads to the first bonding pads;
• and
• a second bonding wire structure connecting the center pads to the second bonding pads,
• wherein a distance between the second bonding pads and the at least one controller is greater than a distance between the first bonding pads and the at least one controller.

A semiconductor package comprising:

• a substrate including first bonding pads, second bonding pads, and third bonding pads;
• at least two chip structures disposed on the substrate to be spaced apart from each other in a first direction, the at least two chip structures each including a plurality of semiconductor chips respectively including pads;
• at least one controller disposed between the at least two chip structures on the substrate, the at least one controller having an upper surface on which edge pads arranged in at least two columns in a second direction, perpendicular to the first direction, and center pads arranged in at least one column in the second direction between the edge pads on opposite sides;
• a first bonding wire structure connecting the edge pads to the first bonding pads;
• a second bonding wire structure connecting the center pads to the second bonding pads;
• and
• a third bonding wire structure connecting the at least two chip structures to the third bonding pads,
• wherein at least a set of the third bonding pads include first and second bonding fingers spaced apart from each other in the first direction,
• wherein the third bonding wire structure includes:
• lower wires directly connecting lower semiconductor chips of the plurality of semiconductor chips and the first bonding fingers to each other, and
• upper wires directly connecting upper semiconductor chips of the plurality of semiconductor chips and the second bonding fingers to each other.