Semiconductor device and method of fabricating the same

A semiconductor device comprising:

• a first active pattern and a second active pattern spaced apart from each other in a first direction and extending in a second direction on a substrate having a top surface and a bottom surface opposite the top surface, the first direction and the second direction being parallel to the top surface of the substrate and intersecting each other;
• a device isolation layer between the first active pattern and the second active pattern;
• a first channel pattern on the first active pattern;
• a second channel pattern on the second active pattern;
• a first gate electrode extending in the first direction and crossing the first active pattern and the first channel pattern;
• a second gate electrode extending in the first direction and crossing the second active pattern and the second channel pattern;
• and
• a separation insulating pattern interposed between the first gate electrode and the second gate electrode and disposed on the device isolation layer,
• wherein the first gate electrode and the second gate electrode are aligned with each other in the first direction,
• wherein the separation insulating pattern includes a lower pattern and an upper pattern stacked in a third direction perpendicular to the top surface of the substrate, and
• wherein a top surface of the lower pattern is positioned at a lower height than an uppermost surface of the first channel pattern and an uppermost surface of the second channel pattern.

A semiconductor device comprising:

• a first active pattern and a second active pattern spaced apart from each other in a first direction and extending in a second direction on a substrate having a top surface and a bottom surface opposite the top surface, the first direction and the second direction being parallel to the top surface of the substrate and intersecting each other;
• a first channel pattern on the first active pattern;
• first source/drain patterns on the first active pattern and spaced apart from each other in the second direction across the first channel pattern;
• a second channel pattern on the second active pattern;
• second source/drain patterns on the second active pattern and spaced apart from each other in the second direction across the second channel pattern;
• a first gate electrode extending in the first direction and crossing the first active pattern and the first channel pattern;
• a second gate electrode extending in the first direction and crossing the second active pattern and the second channel pattern;
• and
• a separation insulating pattern interposed between the first gate electrode and the second gate electrode,
• wherein the first gate electrode and the second gate electrode are aligned with each other in the first direction,
• wherein the separation insulating pattern includes a lower pattern and an upper pattern stacked in a third direction perpendicular to the top surface of the substrate,
• wherein an interface between the lower pattern and the upper pattern is located at a lower height than an uppermost surface of the first channel pattern and an uppermost surface of the second channel pattern, and
• wherein the first source/drain patterns have a different conductivity type than the second source/drain patterns.