Deep trench isolation structures and methods of forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorYen Chang Tseng
Life of this patent
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Abstract
A Deep Trench Insulator (DTI) structure and method of forming the same including forming one or more deep trench isolation (DTI) structures on one or more STI structures, each of the DTI structures including a DTI trench depth extending from a DTI trench top to a DTI trench bottom, and the DTI trench formed to extend entirely through the STI trench bottom. Furthermore, according to another example DTI structure, the DTI structure includes one or more deep trench isolation (DTI) polygonal ring shaped structures, each of the DTI polygonal ring shaped structure having a DTI trench including a DTI trench depth extending from a DTI trench top to the DTI trench bottom.
Claims20
A method of forming a deep trench isolation structure in a semiconductor substrate comprising:
- forming an active region in a semiconductor substrate, the active region including one or more transistor regions having gate, source and drain regions, and one or more N-type or P-type doped isolation regions laterally adjacent to the active region/area;
- forming a plurality of shallow trench isolation (STI) structures in one or both of the active region and the one or more isolation regions, the STI structures each having a STI trench including a STI trench top, a STI trench bottom, STI trench sidewalls and a STI trench depth extending from the STI trench top to the STI trench bottom;
- and
- forming one or more deep trench isolation (DTI) structures on at least one of the STI structures, each of the DTI structures including a DTI trench having a DTI trench top, a DTI trench bottom, DTI trench sidewalls, a DTI trench depth extending from the DTI trench top to the DTI trench bottom, and the DTI trench formed to extend entirely through the STI trench bottom.
A semiconductor device comprising:
- a semiconductor substrate;
- an active region formed on the semiconductor substrate, the active region including one or more transistor regions having gate, source and drain regions,
- one or more N-type or P-type doped isolation regions laterally adjacent to the active region/area;
- a plurality of shallow trench isolation (STI) structures in one or both of the active region and the one or more isolation regions, the STI structures each having a STI trench including a STI trench top, a STI trench bottom, STI trench sidewalls and a STI trench depth extending from the STI trench top to the STI trench bottom;
- and
- one or more deep trench isolation (DTI) structures on at least one of the STI structures, each of the DTI structures including a DTI trench having a DTI trench top, a DTI trench bottom, DTI trench sidewalls, a DTI trench depth extending from the DTI trench top to the DTI trench bottom, and the DTI trench formed to extend entirely through the STI trench bottom.
A method of forming an integrated circuit (IC) including a deep trench isolation structure in a semiconductor substrate comprising:
- forming a plurality of shallow trench isolation (STI) structures in one or both of an active region of the semiconductor substrate, and one or more isolation regions of the semiconductor substrate, the STI structures each having a STI trench including a STI trench top, a STI trench bottom, STI trench sidewalls and a STI trench depth extending from the STI trench top to the STI trench bottom;
- and
- forming one or more deep trench isolation (DTI) polygonal ring shaped structures, the DTI polygonal ring shaped structure each having a DTI trench including a DTI trench top width, a DTI trench bottom, DTI trench sidewalls, and a DTI trench depth extending from the DTI trench top to the DTI trench bottom.
Dependencies are inferred from the claim text.