Integrated circuit device

An integrated circuit device comprising:

• first and second semiconductor regions, which extend in a first horizontal direction and are adjacent to one another in a second horizontal direction orthogonal to the first horizontal direction;
• an insulating wall structure extending in the first horizontal direction between the first and second semiconductor regions;
• first and second nanosheet stacks positioned to respectively overlap the first and second semiconductor regions in a vertical direction and spaced apart from one another in the second horizontal direction with the insulating wall structure therebetween, each of the first and second nanosheet stacks comprising at least one nanosheet;
• a first gate line arranged over the first semiconductor region to surround the at least one nanosheet of the first nanosheet stack;
• a first gate dielectric film surrounding the first gate line and comprising a first end portion that is adjacent to a first sidewall of the insulating wall structure in the second horizontal direction;
• a first source/drain region positioned adjacent to the first gate line and contacting the at least one nanosheet of the first nanosheet stack, the first source/drain region being in contact with the first sidewall of the insulating wall structure;
• and
• a first blocking insulating spacer, in a plan view, arranged in a first gap area between the insulating wall structure and the first gate line in the second horizontal direction and contacting the first source/drain region,
• wherein the first blocking insulating spacer comprises, in the first gap area, a portion contacting the first end portion of the first gate dielectric film and a portion contacting the first sidewall of the insulating wall structure.

An integrated circuit device comprising:

• a fin-type active region extending in a first horizontal direction;
• a device isolation film covering both sidewalls of the fin-type active region in a second horizontal direction intersecting the first horizontal direction;
• a nanosheet stack comprising a plurality of nanosheets arranged over the fin-type active region;
• a gate line arranged over the fin-type active region to surround the plurality of nanosheets and overlapping a portion of the device isolation film in a vertical direction;
• a source/drain region arranged on the fin-type active region and contacting the plurality of nanosheets;
• an insulating wall structure having a first sidewall that, in the second horizontal direction, faces each of the source/drain region, the gate line, and the plurality of nanosheets;
• a gate dielectric film surrounding the gate line;
• and
• a blocking insulating spacer, in a plan view, arranged in a gap area between the first sidewall of the insulating wall structure and the gate line, in the second horizontal direction, and contacting the source/drain region,
• wherein the blocking insulating spacer comprises, in the gap area, a portion contacting the gate dielectric film and a portion contacting the first sidewall of the insulating wall structure,
• a minimum separation width in the second horizontal direction between the plurality of nanosheets and the first sidewall of the insulating wall structure is a first width, and
• a minimum separation width between the first sidewall of the insulating wall structure and the gate line that is between each of the plurality of nanosheets is less than the first width.