Semiconductor structure including gate electrode doped with stressor element and method for manufacturing the same

A method for manufacturing a semiconductor structure, comprising:

• forming an active region over a substrate;
• forming an isolation structure over the substrate and around a lower portion of the active region;
• and
• forming a gate structure extending along surfaces of an upper portion of the active region and a top surface of the isolation structure, the gate structure having a curved top surface, the gate structure including a gate dielectric layer and a gate electrode over the gate dielectric layer, the gate electrode including a work function layer, the work function layer including a work function material and a stressor element doped in the work function material, the stressor element including a metal element that is different from a metal element in the work function material, the stressor element being present in an amount sufficient to permit the work function layer to apply a stress on the upper portion of the active region.

A method for manufacturing a semiconductor structure, comprising:

• forming a first channel region and a second channel region over a substrate and extending lengthwise along a direction;
• forming an isolation structure over the substrate and between the first channel region and the second channel region, a top surface of the isolation structure is non-planar when viewed along the direction;
• and
• forming a gate structure extending along surfaces of the first channel region, the second channel region and a top surface of the isolation structure, the gate structure including a gate dielectric layer and a gate electrode over the gate dielectric layer, the gate electrode including
• a first work function layer disposed on the first channel region and separated from the first channel region by a first portion of the gate dielectric layer, the first work function layer including a first work function material and a first stressor element doped in the first work function material, so as to generate a tensile stress to be applied on the first channel region, the first stressor element including a metal element that is different from a metal element in the first work function material, and
• a second work function layer disposed on the second channel region and separated from the second channel region by a second portion of the gate dielectric layer, the second work function layer including a second work function material and a second stressor element doped in the second work function material, so as to generate a compressive stress to be applied on the second channel region, the second stressor element including a metal element that is different from a metal element in the second work function material,
• an atomic radius of the first stressor element being smaller than an atomic radius of the second stressor element.