Gate etch back with reduced loading effect

A semiconductor device, comprising:

• a substrate;
• a first gate electrode over the substrate and comprising:
• a first metal layer having a first topmost surface height with respect to a top surface of the substrate;
• and
• a second metal layer over the first metal layer and having a second topmost surface height with respect to the top surface of the substrate;
• and
• a second gate electrode over the substrate and comprising:
• a third metal layer and having a third topmost surface height with respect to the top surface of the substrate;
• and
• a fourth metal layer over the third metal layer and having a fourth topmost surface height with respect to the top surface of the substrate, wherein a difference between the first topmost surface height and the third topmost surface height is less than a difference between the second topmost surface height and the fourth topmost surface height.

A semiconductor device, comprising:

• a substrate;
• a first gate structure over the substrate, wherein the first gate structure comprising:
• a first gate dielectric layer;
• a first metal layer over the first gate dielectric layer;
• and
• a second metal layer over the first metal layer;
• and
• a gate cap over the first gate structure and interfacing with the second metal layer, wherein the second metal layer has a top profile that includes two local peaks, and wherein the gap cap interfaces opposite sides of each of the two local peaks.