US 2026/0271359 A1Published application

Semiconductor structure and methods of forming the same

AssigneeNanya Technology Corporation

InventorsYen-Ho CHU, Weng Yiang THAM

Life of this patent

Estimating the term…

Loading patent…

Abstract

The disclosure provides a method of forming a semiconductor structure, including forming a gate structure on a substrate, depositing a first dielectric material on the gate structure, performing a first implantation process to implant the substrate with a uniform top surface to form a first doping region in the substrate, performing a second implantation process to implant the substrate with the uniform top surface to form a second doping region in the substrate, depositing a second dielectric material on the first dielectric material, etching a portion of the first dielectric material, the second dielectric material and the substrate to form recesses in the substrate, performing a third implantation process to implant the recesses to form a third doping region in the substrate, and performing an anneal process.

Claims16

Dependent claims

A method of forming a semiconductor structure, comprising:

forming a gate structure on a substrate;
depositing conformally a first dielectric material on the gate structure and the substrate;
performing a first implantation process to implant the substrate with a first doping species to form a first doping region in the substrate, wherein a top surface of the substrate is uniform;
performing a second implantation process to implant the substrate with a second doping species opposite to the first doping species to form a second doping region in the substrate, wherein the top surface of the substrate is uniform;
depositing a second dielectric material on the first dielectric material;
etching a portion of the first dielectric material, the second dielectric material and the substrate to form recesses in the substrate;
performing a third implantation process to implant the recesses in the substrate with a third doping species to form a third doping region in the substrate, wherein the third doping species is the same species as the second doping species;
and
performing an anneal process.

6 more elements

A semiconductor structure, comprising:

a gate structure on a substrate;
spacers, each of the spacers comprising:
a first portion along sidewalls of the gate structure;
and
a second portion on the substrate and connected to an end of the first portion;
a second dielectric layer on the spacers and adjacent the first portions and the second portions;
recesses exposed in a top portion of the substrate and laterally surrounding the gate structure, the spacers and the second dielectric layer;
a first doping region with a first doping species in the substrate, comprising:
a width between a top surface and a bottom surface of the first doping region in a range from 18.2 to 33.8 nm;
a distance between the top surface of the first doping region and a top surface of the substrate in a range from 16.1 to 23.9 nm;
a distance between the bottom surface of the first doping region and the top surface of the substrate in a range from 42.1 to 49.9 nm;
and
a highest doping concentration at a depth below the top surface of the substrate in a range from 30 to 36 nm;
a second doping region with a second doping species opposite to the first doping species in the substrate below the second portion, comprising:
a width between a top surface and a bottom surface of the second doping region in a range from 1.6 to 2.8 nm;
a distance between the top surface of the second doping region and the top surface of the substrate in a range from 1.6 to 2.2 nm;
a distance between the bottom surface of the second doping region and the top surface of the substrate in a range from 3.8 to 4.4 nm;
and
a highest doping concentration at a depth below the top surface of the substrate in a range from 2.75 to 3.25 nm;
and
a third doping region with a third doping species in the substrate below the recesses, wherein the third doping region is overlapping partially with the first doping region.

18 more elements

Dependencies are inferred from the claim text.

Facts

Application: 19/069,238Filed 4 Mar 2025
Published: 10 Sep 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10D 62/60
Semiconductor bodies, or regions thereof, of devices having potential barriers: impurity distributions or concentrations
H10D 64/021
Manufacture or treatment: using multiple gate spacer layers, e.g. bilayered sidewall spacers
H10D 30/0218
Of FETs having insulated gates [IGFET]: having pocket halo regions selectively formed at the sides of the gates
H10D 30/022
Of FETs having insulated gates [IGFET]: having lightly-doped source or drain extensions selectively formed at the sides of the gates