Semiconductor/dielectric interface engineering for iii-n transistors

An integrated circuit (IC) structure, comprising:

• a first semiconductor material comprising gallium and nitrogen, wherein a portion of the first semiconductor material is a channel region of a transistor;
• a stack of materials over the first semiconductor material, wherein the stack comprises:
• a second semiconductor material over the first semiconductor material, wherein the second semiconductor material has a different material composition than the first semiconductor material,
• an insulator material over the second semiconductor material, and
• a third semiconductor material between the insulator material and the second semiconductor material;
• and
• a gate structure over the portion of the first semiconductor material and in the stack, wherein the gate structure comprises an electrically conductive material coplanar with the second semiconductor material, the insulator material, and the third semiconductor material.

A method of fabricating an integrated circuit (IC) structure, comprising:

• providing a layer of a first semiconductor material comprising gallium and nitrogen over a substrate;
• providing a second semiconductor material over the first semiconductor material;
• providing an insulator material over the second semiconductor material;
• forming an opening in the insulator material and the second semiconductor material, wherein the first semiconductor material is exposed at a bottom of the opening;
• providing another material on the first semiconductor material at the bottom of the opening;
• providing a gate dielectric material on the other material and on sidewalls of the opening;
• and
• providing a gate electrode material in the opening over the gate dielectric material.